diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-07 15:00:18 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-12 15:45:37 +0100 |
| commit | 84d20d0eb3869d7babaeed7cfbe53f9edad48850 (patch) | |
| tree | 6a5d37792281c6c70d17ef925a250535bc236d9f /src/include/device | |
| parent | 91d1e76fd168defce4132d1e308b68a2013a89df (diff) | |
src/include: Remove spaces before tabs
Fix the following warning detected by checkpatch.pl:
WARNING: please, no space before tabs
TEST=Build and run on Galileo Gen2
Change-Id: If60a58021d595289722d1d6064bea37b0b0bc039
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18652
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/device.h | 6 | ||||
| -rw-r--r-- | src/include/device/pci_def.h | 10 | ||||
| -rw-r--r-- | src/include/device/pci_ehci.h | 2 | ||||
| -rw-r--r-- | src/include/device/pci_ids.h | 4 |
4 files changed, 11 insertions, 11 deletions
diff --git a/src/include/device/device.h b/src/include/device/device.h index 6fcb9ae8a4..e60277d720 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -82,13 +82,13 @@ static inline void device_noop(struct device *dev) {} struct bus { - ROMSTAGE_CONST struct device * dev; /* This bridge device */ - ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ + ROMSTAGE_CONST struct device * dev; /* This bridge device */ + ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ unsigned int bridge_ctrl; /* Bridge control register */ uint16_t bridge_cmd; /* Bridge command register */ unsigned char link_num; /* The index of this link */ - uint16_t secondary; /* secondary bus number */ + uint16_t secondary; /* secondary bus number */ uint16_t subordinate; /* max subordinate bus number */ unsigned char cap; /* PCi capability offset */ uint32_t hcdn_reg; /* For HyperTransport link */ diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index e11470c695..a1236eff2d 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -15,7 +15,7 @@ #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ -#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ +#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ #define PCI_COMMAND_INT_DISABLE 0x400 /* Interrupt disable */ @@ -183,7 +183,7 @@ #define PCI_CAP_ID_PCIX 0x07 /* PCIX */ #define PCI_CAP_ID_HT 0x08 /* Hypertransport */ #define PCI_CAP_ID_EHCI_DEBUG 0x0A /* EHCI debug port */ -#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ +#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ #define PCI_CAP_ID_PCIE 0x10 /* PCI Express */ #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ @@ -243,8 +243,8 @@ #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ -#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ -#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ +#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ +#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ @@ -289,7 +289,7 @@ #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ -#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ +#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ #define PCI_X_STATUS 4 /* PCI-X capabilities */ #define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */ #define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h index 42e1d8365f..4a89a60852 100644 --- a/src/include/device/pci_ehci.h +++ b/src/include/device/pci_ehci.h @@ -21,7 +21,7 @@ #include <device/device.h> #define EHCI_BAR_INDEX 0x10 -#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ +#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx); u8 *pci_ehci_base_regs(pci_devfn_t dev); diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 7d59415931..023238753f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -598,7 +598,7 @@ #define PCI_DEVICE_ID_AMD_8111_IDE 0x7469 #define PCI_DEVICE_ID_AMD_8111_SMB 0x746a #define PCI_DEVICE_ID_AMD_8111_ACPI 0x746b -#define PCI_DEVICE_ID_AMD_8111_NIC 0x7462 +#define PCI_DEVICE_ID_AMD_8111_NIC 0x7462 #define PCI_DEVICE_ID_AMD_8111_USB2 0x7463 #define PCI_DEVICE_ID_AMD_8131_PCIX 0x7450 @@ -2743,7 +2743,7 @@ #define PCI_DEVICE_ID_MICROGATE_SCA 0x0030 #define PCI_VENDOR_ID_SIS 0x1039 -#define PCI_DEVICE_ID_SIS_AGP 0x0002 +#define PCI_DEVICE_ID_SIS_AGP 0x0002 /* SiS 761GX NORTH BRIDGE */ #define PCI_DEVICE_ID_SIS_SIS761 0x0761 |