eric patch

        1. x86_setup_mtrr take address bit.
        2. generic ht, pcix, pcie beidge...
        3. scan bus and reset_bus
        4. ht read ctrl to decide if the ht chain
           is ready
        5. Intel e7520 and e7525 support
        6. new ich5r support
        7. intel sb 6300 support.

yhlu patch
	1. split x86_setup_mtrrs to fixed and var
	2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
	3. in_conherent.c K8_SCAN_PCI_BUS


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

11 files changed, 315 insertions, 22 deletions

diff --git a/src/include/device/agp.h b/src/include/device/agp.h
new file mode 100644
index 0000000000..073858ae10
--- /dev/null
+++ b/src/include/device/agp.h
@@ -0,0 +1,12 @@
+#ifndef DEVICE_AGP_H
+#define DEVICE_AGP_H
+/* (c) 2005 Linux Networx GPL see COPYING for details */
+
+unsigned int agp_scan_bus(struct bus *bus, 
+	unsigned min_devfn, unsigned max_devfn, unsigned int max);
+unsigned int agp_scan_bridge(device_t dev, unsigned int max);
+
+extern struct device_operations default_agp_ops_bus;
+
+
+#endif /* DEVICE_AGP_H */
diff --git a/src/include/device/cardbus.h b/src/include/device/cardbus.h
new file mode 100644
index 0000000000..38aa41cab5
--- /dev/null
+++ b/src/include/device/cardbus.h
@@ -0,0 +1,12 @@
+#ifndef DEVICE_CARDBUS_H
+#define DEVICE_CARDBUS_H
+/* (c) 2005 Linux Networx GPL see COPYING for details */
+
+void cardbus_read_resources(device_t dev);
+unsigned int cardbus_scan_bus(struct bus *bus, 
+	unsigned min_devfn, unsigned max_devfn, unsigned int max);
+unsigned int cardbus_scan_bridge(device_t dev, unsigned int max);
+
+extern struct device_operations default_cardbus_ops_bus;
+
+#endif /* DEVICE_CARDBUS_H */
diff --git a/src/include/device/device.h b/src/include/device/device.h
index be93f554fa..aff5616a88 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -26,6 +26,8 @@ struct chip_operations {
 #define CHIP_NAME(X)
 #endif
 
+struct bus;
+
 struct device_operations {
 	void (*read_resources)(device_t dev);
 	void (*set_resources)(device_t dev);
@@ -34,6 +36,7 @@ struct device_operations {
 	unsigned int (*scan_bus)(device_t bus, unsigned int max);
 	void (*enable)(device_t dev);
 	void (*set_link)(device_t dev, unsigned int link);
+	void (*reset_bus)(struct bus *bus);
 	const struct pci_operations *ops_pci;
 	const struct smbus_bus_operations *ops_smbus_bus;
 	const struct pci_bus_operations *ops_pci_bus;
@@ -48,6 +51,8 @@ struct bus {
 	unsigned char	secondary; 	/* secondary bus number */
 	unsigned char	subordinate;	/* max subordinate bus number */
 	unsigned char   cap;		/* PCi capability offset */
+	unsigned	reset_needed : 1;
+	unsigned	disable_relaxed_ordering : 1;
 };
 
 #define MAX_RESOURCES 12
@@ -81,7 +86,8 @@ struct device {
 	unsigned int resources;
 
 	/* link are (down sream) buses attached to the device, usually a leaf
-	 * device with no child have 0 bus attached and a bridge has 1 bus */
+	 * device with no children have 0 buses attached and a bridge has 1 bus 
+	 */
 	struct bus link[MAX_LINKS];
 	/* number of buses attached to the device */
 	unsigned int links;
@@ -101,8 +107,11 @@ extern void dev_enumerate(void);
 extern void dev_configure(void);
 extern void dev_enable(void);
 extern void dev_initialize(void);
+extern void dev_optimize(void);
 
 /* Generic device helper functions */
+extern int reset_bus(struct bus *bus);
+extern unsigned int scan_bus(struct device *bus, unsigned int max);
 extern void compute_allocate_resource(struct bus *bus, struct resource *bridge,
 	unsigned long type_mask, unsigned long type);
 extern void assign_resources(struct bus *bus);
@@ -110,6 +119,9 @@ extern void enable_resources(struct device *dev);
 extern void enumerate_static_device(void);
 extern void enumerate_static_devices(void);
 extern const char *dev_path(device_t dev);
+const char *bus_path(struct bus *bus);
+extern void dev_set_enabled(device_t dev, int enable);
+extern void disable_children(struct bus *bus);
 
 /* Helper functions */
 device_t find_dev_path(struct bus *parent, struct device_path *path);
@@ -134,5 +146,4 @@ extern void enable_childrens_resources(device_t dev);
 extern void root_dev_enable_resources(device_t dev);
 extern unsigned int root_dev_scan_bus(device_t root, unsigned int max);
 extern void root_dev_init(device_t dev);
-
 #endif /* DEVICE_H */
diff --git a/src/include/device/hypertransport.h b/src/include/device/hypertransport.h
index 410495cdcb..f04d0eca30 100644
--- a/src/include/device/hypertransport.h
+++ b/src/include/device/hypertransport.h
@@ -3,7 +3,10 @@
 
 #include <device/hypertransport_def.h>
 
-unsigned int hypertransport_scan_chain(struct bus *bus, unsigned int max);
+unsigned int hypertransport_scan_chain(struct bus *bus, 
+	unsigned min_devfn, unsigned max_devfn, unsigned int max);
+unsigned int ht_scan_bridge(struct device *dev, unsigned int max);
+extern struct device_operations default_ht_ops_bus;
 
 #define HT_IO_HOST_ALIGN 4096
 #define HT_MEM_HOST_ALIGN (1024*1024)
diff --git a/src/include/device/path.h b/src/include/device/path.h
index f55827b9c0..cfac751e26 100644
--- a/src/include/device/path.h
+++ b/src/include/device/path.h
@@ -72,6 +72,7 @@ struct device_path {
 
 
 #define DEVICE_PATH_MAX 30
+#define BUS_PATH_MAX (DEVICE_PATH_MAX+10)
 
 extern int path_eq(struct device_path *path1, struct device_path *path2);
 
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index d359a96666..2daa1ca03e 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -50,16 +50,26 @@ extern struct pci_driver pci_drivers[];
 extern struct pci_driver epci_drivers[];
 
 
-struct device_operations default_pci_ops_dev;
-struct device_operations default_pci_ops_bus;
+extern struct device_operations default_pci_ops_dev;
+extern struct device_operations default_pci_ops_bus;
 
 void pci_dev_read_resources(device_t dev);
 void pci_bus_read_resources(device_t dev);
 void pci_dev_set_resources(device_t dev);
 void pci_dev_enable_resources(device_t dev);
 void pci_bus_enable_resources(device_t dev);
+void pci_bus_reset(struct bus *bus);
+device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn);
+unsigned int do_pci_scan_bridge(device_t bus, unsigned int max,
+	unsigned int (*do_scan_bus)(struct bus *bus, 
+		unsigned min_devfn, unsigned max_devfn, unsigned int max));
 unsigned int pci_scan_bridge(device_t bus, unsigned int max);
 unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max);
+uint8_t pci_moving_config8(struct device *dev, unsigned reg);
+uint16_t pci_moving_config16(struct device *dev, unsigned reg);
+uint32_t pci_moving_config32(struct device *dev, unsigned reg);
+unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last);
+unsigned pci_find_capability(device_t dev, unsigned cap);
 struct resource *pci_get_resource(struct device *dev, unsigned long index);
 void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device);
 
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index dc2176babb..6fb7ebd385 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -181,15 +181,20 @@
 #define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
 #define  PCI_CAP_ID_PCIX	0x07	/* PCIX  */
 #define  PCI_CAP_ID_HT          0x08	/* Hypertransport */
+#define  PCI_CAP_ID_SHPC 	0x0C	/* PCI Standard Hot-Plug Controller */
 #define  PCI_CAP_ID_PCIE	0x10	/* PCI Express */
+#define  PCI_CAP_ID_MSIX	0x11	/* MSI-X */
 #define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
 #define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
 
 /* Hypertransport Registers */
 #define PCI_HT_CAP_SIZEOF	   4
+#define PCI_HT_CAP_HOST_CTRL       4	/* Host link control */ 
 #define PCI_HT_CAP_HOST_WIDTH	   6	/* width value & capability  */
 #define PCI_HT_CAP_HOST_FREQ	   0x09	/* Host frequency */
 #define PCI_HT_CAP_HOST_FREQ_CAP   0x0a	/* Host Frequency capability  */
+#define PCI_HT_CAP_SLAVE_CTRL0	   4	/* link control */
+#define PCI_HT_CAP_SLAVE_CTRL1	   8	/* link control to */
 #define PCI_HT_CAP_SLAVE_WIDTH0	   6	/* width value & capability  */
 #define PCI_HT_CAP_SLAVE_WIDTH1	   0x0a	/* width value & capability  to */
 #define PCI_HT_CAP_SLAVE_FREQ0	   0x0d	/* Slave frequency from */
@@ -199,6 +204,7 @@
 
 /* Power Management Registers */
 
+#define PCI_PM_PMC              2       /* PM Capabilities Register */
 #define  PCI_PM_CAP_VER_MASK	0x0007	/* Version */
 #define  PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
 #define  PCI_PM_CAP_AUX_POWER	0x0010	/* Auxilliary power support */
@@ -260,6 +266,191 @@
 #define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
 #define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
 #define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
+#define PCI_MSI_MASK_BIT	16	/* Mask bits register */
+
+/* CompactPCI Hotswap Register */
+
+#define PCI_CHSWP_CSR		2	/* Control and Status Register */
+#define  PCI_CHSWP_DHA		0x01	/* Device Hiding Arm */
+#define  PCI_CHSWP_EIM		0x02	/* ENUM# Signal Mask */
+#define  PCI_CHSWP_PIE		0x04	/* Pending Insert or Extract */
+#define  PCI_CHSWP_LOO		0x08	/* LED On / Off */
+#define  PCI_CHSWP_PI		0x30	/* Programming Interface */
+#define  PCI_CHSWP_EXT		0x40	/* ENUM# status - extraction */
+#define  PCI_CHSWP_INS		0x80	/* ENUM# status - insertion */
+
+/* PCI-X registers */
+
+#define PCI_X_CMD		2	/* Modes & Features */
+#define  PCI_X_CMD_DPERR_E	0x0001	/* Data Parity Error Recovery Enable */
+#define  PCI_X_CMD_ERO		0x0002	/* Enable Relaxed Ordering */
+#define  PCI_X_CMD_MAX_READ	0x000c	/* Max Memory Read Byte Count */
+#define  PCI_X_CMD_MAX_SPLIT	0x0070	/* Max Outstanding Split Transactions */
+#define  PCI_X_CMD_VERSION(x) 	(((x) >> 12) & 3) /* Version */
+#define PCI_X_STATUS		4	/* PCI-X capabilities */
+#define  PCI_X_STATUS_DEVFN	0x000000ff	/* A copy of devfn */
+#define  PCI_X_STATUS_BUS	0x0000ff00	/* A copy of bus nr */
+#define  PCI_X_STATUS_64BIT	0x00010000	/* 64-bit device */
+#define  PCI_X_STATUS_133MHZ	0x00020000	/* 133 MHz capable */
+#define  PCI_X_STATUS_SPL_DISC	0x00040000	/* Split Completion Discarded */
+#define  PCI_X_STATUS_UNX_SPL	0x00080000	/* Unexpected Split Completion */
+#define  PCI_X_STATUS_COMPLEX	0x00100000	/* Device Complexity */
+#define  PCI_X_STATUS_MAX_READ	0x00600000	/* Designed Max Memory Read Count */
+#define  PCI_X_STATUS_MAX_SPLIT	0x03800000	/* Designed Max Outstanding Split Transactions */
+#define  PCI_X_STATUS_MAX_CUM	0x1c000000	/* Designed Max Cumulative Read Size */
+#define  PCI_X_STATUS_SPL_ERR	0x20000000	/* Rcvd Split Completion Error Msg */
+#define  PCI_X_STATUS_266MHZ	0x40000000	/* 266 MHz capable */
+#define  PCI_X_STATUS_533MHZ	0x80000000	/* 533 MHz capable */
+
+/* PCI-X bridge registers */
+#define PCI_X_SEC_STATUS	2	/* Secondary status */
+#define  PCI_X_SSTATUS_64BIT	0x0001	/* The bus behind the bridge is 64bits wide */
+#define  PCI_X_SSTATUS_133MHZ	0x0002	/* The bus behind the bridge is 133Mhz Capable */
+#define  PCI_X_SSTATUS_SPL_DISC 0x0004	/* Split Completion Discarded */
+#define  PCI_X_SSTATUS_UNX_SPL	0x0008	/* Unexpected Split Completion */
+#define  PCI_X_SSTATUS_SPL_OVR	0x0010	/* Split Completion Overrun */
+#define  PCI_X_SSTATUS_SPL_DLY	0x0020	/* Split Completion Delayed */
+#define  PCI_X_SSTATUS_MFREQ(x) (((x) & 0x03c0) >> 6)	/* PCI-X mode and frequency */
+#define   PCI_X_SSTATUS_CONVENTIONAL_PCI	0x0
+#define   PCI_X_SSTATUS_MODE1_66MHZ	0x1
+#define   PCI_X_SSTATUS_MODE1_100MHZ	0x2
+#define   PCI_X_SSTATUS_MODE1_133MHZ	0x3
+#define   PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ	0x9
+#define   PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ	0xa
+#define   PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ	0xb
+#define   PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ	0xd
+#define   PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ	0xe
+#define   PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ	0xf
+#define  PCI_X_SSTATUS_VERSION(x)	(((x) >> 12) & 3) /* Version */
+#define  PCI_X_SSTATUS_266MHZ	0x4000	/* The bus behind the bridge is 266Mhz Capable */
+#define  PCI_X_SSTAUTS_533MHZ	0x8000	/* The bus behind the bridge is 533Mhz Capable */
+
+/* PCI Express capability registers */
+
+#define PCI_EXP_FLAGS		2	/* Capabilities register */
+#define PCI_EXP_FLAGS_VERS	0x000f	/* Capability version */
+#define PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
+#define  PCI_EXP_TYPE_ENDPOINT	0x0	/* Express Endpoint */
+#define  PCI_EXP_TYPE_LEG_END	0x1	/* Legacy Endpoint */
+#define  PCI_EXP_TYPE_ROOT_PORT 0x4	/* Root Port */
+#define  PCI_EXP_TYPE_UPSTREAM	0x5	/* Upstream Port */
+#define  PCI_EXP_TYPE_DOWNSTREAM 0x6	/* Downstream Port */
+#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7	/* PCI/PCI-X Bridge */
+#define PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
+#define PCI_EXP_FLAGS_IRQ	0x3e00	/* Interrupt message number */
+#define PCI_EXP_DEVCAP		4	/* Device capabilities */
+#define  PCI_EXP_DEVCAP_PAYLOAD	0x07	/* Max_Payload_Size */
+#define  PCI_EXP_DEVCAP_PHANTOM	0x18	/* Phantom functions */
+#define  PCI_EXP_DEVCAP_EXT_TAG	0x20	/* Extended tags */
+#define  PCI_EXP_DEVCAP_L0S	0x1c0	/* L0s Acceptable Latency */
+#define  PCI_EXP_DEVCAP_L1	0xe00	/* L1 Acceptable Latency */
+#define  PCI_EXP_DEVCAP_ATN_BUT	0x1000	/* Attention Button Present */
+#define  PCI_EXP_DEVCAP_ATN_IND	0x2000	/* Attention Indicator Present */
+#define  PCI_EXP_DEVCAP_PWR_IND	0x4000	/* Power Indicator Present */
+#define  PCI_EXP_DEVCAP_PWR_VAL	0x3fc0000 /* Slot Power Limit Value */
+#define  PCI_EXP_DEVCAP_PWR_SCL	0xc000000 /* Slot Power Limit Scale */
+#define PCI_EXP_DEVCTL		8	/* Device Control */
+#define  PCI_EXP_DEVCTL_CERE	0x0001	/* Correctable Error Reporting En. */
+#define  PCI_EXP_DEVCTL_NFERE	0x0002	/* Non-Fatal Error Reporting Enable */
+#define  PCI_EXP_DEVCTL_FERE	0x0004	/* Fatal Error Reporting Enable */
+#define  PCI_EXP_DEVCTL_URRE	0x0008	/* Unsupported Request Reporting En. */
+#define  PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
+#define  PCI_EXP_DEVCTL_PAYLOAD	0x00e0	/* Max_Payload_Size */
+#define  PCI_EXP_DEVCTL_EXT_TAG	0x0100	/* Extended Tag Field Enable */
+#define  PCI_EXP_DEVCTL_PHANTOM	0x0200	/* Phantom Functions Enable */
+#define  PCI_EXP_DEVCTL_AUX_PME	0x0400	/* Auxiliary Power PM Enable */
+#define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
+#define  PCI_EXP_DEVCTL_READRQ	0x7000	/* Max_Read_Request_Size */
+#define PCI_EXP_DEVSTA		10	/* Device Status */
+#define  PCI_EXP_DEVSTA_CED	0x01	/* Correctable Error Detected */
+#define  PCI_EXP_DEVSTA_NFED	0x02	/* Non-Fatal Error Detected */
+#define  PCI_EXP_DEVSTA_FED	0x04	/* Fatal Error Detected */
+#define  PCI_EXP_DEVSTA_URD	0x08	/* Unsupported Request Detected */
+#define  PCI_EXP_DEVSTA_AUXPD	0x10	/* AUX Power Detected */
+#define  PCI_EXP_DEVSTA_TRPND	0x20	/* Transactions Pending */
+#define PCI_EXP_LNKCAP		12	/* Link Capabilities */
+#define PCI_EXP_LNKCTL		16	/* Link Control */
+#define PCI_EXP_LNKSTA		18	/* Link Status */
+#define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
+#define PCI_EXP_SLTCTL		24	/* Slot Control */
+#define PCI_EXP_SLTSTA		26	/* Slot Status */
+#define PCI_EXP_RTCTL		28	/* Root Control */
+#define  PCI_EXP_RTCTL_SECEE	0x01	/* System Error on Correctable Error */
+#define  PCI_EXP_RTCTL_SENFEE	0x02	/* System Error on Non-Fatal Error */
+#define  PCI_EXP_RTCTL_SEFEE	0x04	/* System Error on Fatal Error */
+#define  PCI_EXP_RTCTL_PMEIE	0x08	/* PME Interrupt Enable */
+#define  PCI_EXP_RTCTL_CRSSVE	0x10	/* CRS Software Visibility Enable */
+#define PCI_EXP_RTCAP		30	/* Root Capabilities */
+#define PCI_EXP_RTSTA		32	/* Root Status */
+
+/* Extended Capabilities (PCI-X 2.0 and Express) */
+#define PCI_EXT_CAP_ID(header)		(header & 0x0000ffff)
+#define PCI_EXT_CAP_VER(header)		((header >> 16) & 0xf)
+#define PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)
+
+#define PCI_EXT_CAP_ID_ERR	1
+#define PCI_EXT_CAP_ID_VC	2
+#define PCI_EXT_CAP_ID_DSN	3
+#define PCI_EXT_CAP_ID_PWR	4
+
+/* Advanced Error Reporting */
+#define PCI_ERR_UNCOR_STATUS	4	/* Uncorrectable Error Status */
+#define  PCI_ERR_UNC_TRAIN	0x00000001	/* Training */
+#define  PCI_ERR_UNC_DLP	0x00000010	/* Data Link Protocol */
+#define  PCI_ERR_UNC_POISON_TLP	0x00001000	/* Poisoned TLP */
+#define  PCI_ERR_UNC_FCP	0x00002000	/* Flow Control Protocol */
+#define  PCI_ERR_UNC_COMP_TIME	0x00004000	/* Completion Timeout */
+#define  PCI_ERR_UNC_COMP_ABORT	0x00008000	/* Completer Abort */
+#define  PCI_ERR_UNC_UNX_COMP	0x00010000	/* Unexpected Completion */
+#define  PCI_ERR_UNC_RX_OVER	0x00020000	/* Receiver Overflow */
+#define  PCI_ERR_UNC_MALF_TLP	0x00040000	/* Malformed TLP */
+#define  PCI_ERR_UNC_ECRC	0x00080000	/* ECRC Error Status */
+#define  PCI_ERR_UNC_UNSUP	0x00100000	/* Unsupported Request */
+#define PCI_ERR_UNCOR_MASK	8	/* Uncorrectable Error Mask */
+	/* Same bits as above */
+#define PCI_ERR_UNCOR_SEVER	12	/* Uncorrectable Error Severity */
+	/* Same bits as above */
+#define PCI_ERR_COR_STATUS	16	/* Correctable Error Status */
+#define  PCI_ERR_COR_RCVR	0x00000001	/* Receiver Error Status */
+#define  PCI_ERR_COR_BAD_TLP	0x00000040	/* Bad TLP Status */
+#define  PCI_ERR_COR_BAD_DLLP	0x00000080	/* Bad DLLP Status */
+#define  PCI_ERR_COR_REP_ROLL	0x00000100	/* REPLAY_NUM Rollover */
+#define  PCI_ERR_COR_REP_TIMER	0x00001000	/* Replay Timer Timeout */
+#define PCI_ERR_COR_MASK	20	/* Correctable Error Mask */
+	/* Same bits as above */
+#define PCI_ERR_CAP		24	/* Advanced Error Capabilities */
+#define  PCI_ERR_CAP_FEP(x)	((x) & 31)	/* First Error Pointer */
+#define  PCI_ERR_CAP_ECRC_GENC	0x00000020	/* ECRC Generation Capable */
+#define  PCI_ERR_CAP_ECRC_GENE	0x00000040	/* ECRC Generation Enable */
+#define  PCI_ERR_CAP_ECRC_CHKC	0x00000080	/* ECRC Check Capable */
+#define  PCI_ERR_CAP_ECRC_CHKE	0x00000100	/* ECRC Check Enable */
+#define PCI_ERR_HEADER_LOG	28	/* Header Log Register (16 bytes) */
+#define PCI_ERR_ROOT_COMMAND	44	/* Root Error Command */
+#define PCI_ERR_ROOT_STATUS	48
+#define PCI_ERR_ROOT_COR_SRC	52
+#define PCI_ERR_ROOT_SRC	54
+
+/* Virtual Channel */
+#define PCI_VC_PORT_REG1	4
+#define PCI_VC_PORT_REG2	8
+#define PCI_VC_PORT_CTRL	12
+#define PCI_VC_PORT_STATUS	14
+#define PCI_VC_RES_CAP		16
+#define PCI_VC_RES_CTRL		20
+#define PCI_VC_RES_STATUS	26
+
+/* Power Budgeting */
+#define PCI_PWR_DSR		4	/* Data Select Register */
+#define PCI_PWR_DATA		8	/* Data Register */
+#define  PCI_PWR_DATA_BASE(x)	((x) & 0xff)	    /* Base Power */
+#define  PCI_PWR_DATA_SCALE(x)	(((x) >> 8) & 3)    /* Data Scale */
+#define  PCI_PWR_DATA_PM_SUB(x)	(((x) >> 10) & 7)   /* PM Sub State */
+#define  PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
+#define  PCI_PWR_DATA_TYPE(x)	(((x) >> 15) & 7)   /* Type */
+#define  PCI_PWR_DATA_RAIL(x)	(((x) >> 18) & 7)   /* Power Rail */
+#define PCI_PWR_CAP		12	/* Capability */
+#define  PCI_PWR_CAP_BUDGET(x)	((x) & 1)	/* Included in system budget */
+
 
 /*
  * The PCI interface treats multi-function devices as independent
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index c0ccdd0fcd..7dba234ba7 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -137,12 +137,14 @@
 #define PCI_DEVICE_ID_COMPAQ_SMART2P	0xae10
 #define PCI_DEVICE_ID_COMPAQ_NETEL100	0xae32
 #define PCI_DEVICE_ID_COMPAQ_NETEL10	0xae34
+#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33
 #define PCI_DEVICE_ID_COMPAQ_NETFLEX3I	0xae35
 #define PCI_DEVICE_ID_COMPAQ_NETEL100D	0xae40
 #define PCI_DEVICE_ID_COMPAQ_NETEL100PI	0xae43
 #define PCI_DEVICE_ID_COMPAQ_NETEL100I	0xb011
 #define PCI_DEVICE_ID_COMPAQ_CISS	0xb060
 #define PCI_DEVICE_ID_COMPAQ_CISSB	0xb178
+#define PCI_DEVICE_ID_COMPAQ_CISSC	0x46
 #define PCI_DEVICE_ID_COMPAQ_THUNDER	0xf130
 #define PCI_DEVICE_ID_COMPAQ_NETFLEX3B	0xf150
 
@@ -165,6 +167,7 @@
 #define PCI_DEVICE_ID_LSI_53C1010_33	0x0020
 #define PCI_DEVICE_ID_LSI_53C1010_66	0x0021
 #define PCI_DEVICE_ID_LSI_53C1030	0x0030
+#define PCI_DEVICE_ID_LSI_1030_53C1035	0x0032
 #define PCI_DEVICE_ID_LSI_53C1035	0x0040
 #define PCI_DEVICE_ID_NCR_53C875J	0x008f
 #define PCI_DEVICE_ID_LSI_FC909		0x0621
@@ -172,9 +175,21 @@
 #define PCI_DEVICE_ID_LSI_FC929_LAN	0x0623
 #define PCI_DEVICE_ID_LSI_FC919		0x0624
 #define PCI_DEVICE_ID_LSI_FC919_LAN	0x0625
+#define PCI_DEVICE_ID_LSI_FC929X	0x0626
+#define PCI_DEVICE_ID_LSI_FC939X	0x0642
+#define PCI_DEVICE_ID_LSI_FC949X	0x0640
+#define PCI_DEVICE_ID_LSI_FC919X	0x0628
 #define PCI_DEVICE_ID_NCR_YELLOWFIN	0x0701
 #define PCI_DEVICE_ID_LSI_61C102	0x0901
 #define PCI_DEVICE_ID_LSI_63C815	0x1000
+#define PCI_DEVICE_ID_LSI_SAS1064	0x0050
+#define PCI_DEVICE_ID_LSI_SAS1066	0x005E
+#define PCI_DEVICE_ID_LSI_SAS1068	0x0054
+#define PCI_DEVICE_ID_LSI_SAS1064A	0x005C
+#define PCI_DEVICE_ID_LSI_SAS1064E	0x0056
+#define PCI_DEVICE_ID_LSI_SAS1066E	0x005A
+#define PCI_DEVICE_ID_LSI_SAS1068E	0x0058
+#define PCI_DEVICE_ID_LSI_SAS1078	0x0060
 
 #define PCI_VENDOR_ID_ATI		0x1002
 /* Mach64 */
@@ -901,6 +916,33 @@
 #define PCI_DEVICE_ID_NVIDIA_UTNT2		0x0029
 #define PCI_DEVICE_ID_NVIDIA_VTNT2		0x002C
 #define PCI_DEVICE_ID_NVIDIA_UVTNT2		0x002D
+#define PCI_DEVICE_ID_NVIDIA_CK804_LPC          0x0050
+#define PCI_DEVICE_ID_NVIDIA_CK804_PRO          0x0051
+#define PCI_DEVICE_ID_NVIDIA_CK804_ISA          0x0051
+#define PCI_DEVICE_ID_NVIDIA_CK804_SMB          0x0052
+#define PCI_DEVICE_ID_NVIDIA_CK804_SM           0x0052
+#define PCI_DEVICE_ID_NVIDIA_CK804_ACPI         0x0052
+#define PCI_DEVICE_ID_NVIDIA_CK804_IDE          0x0053
+#define PCI_DEVICE_ID_NVIDIA_CK804_SATA0        0x0054
+#define PCI_DEVICE_ID_NVIDIA_CK804_SATA1        0x0055
+#define PCI_DEVICE_ID_NVIDIA_CK804_SATA1        0x0055
+#define PCI_DEVICE_ID_NVIDIA_CK804_ENET         0x0056
+#define PCI_DEVICE_ID_NVIDIA_CK804_NIC          0x0056
+#define PCI_DEVICE_ID_NVIDIA_CK804_ENET2        0x0057
+#define PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE   0x0057
+#define PCI_DEVICE_ID_NVIDIA_CK804_MODEM        0x0058
+#define PCI_DEVICE_ID_NVIDIA_CK804_MCI          0x0058
+#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO        0x0059
+#define PCI_DEVICE_ID_NVIDIA_CK804_ACI          0x0059
+#define PCI_DEVICE_ID_NVIDIA_CK804_USB          0x005A
+#define PCI_DEVICE_ID_NVIDIA_CK804_USB2         0x005B
+#define PCI_DEVICE_ID_NVIDIA_CK804_PCI          0x005C
+#define PCI_DEVICE_ID_NVIDIA_CK804_PCIE         0x005D
+#define PCI_DEVICE_ID_NVIDIA_CK804_PCI_E        0x005D
+#define PCI_DEVICE_ID_NVIDIA_CK804_MEM          0x005E
+#define PCI_DEVICE_ID_NVIDIA_CK804_HT           0x005E
+#define PCI_DEVICE_ID_NVIDIA_CK804_TRIM         0x005f
+#define PCI_DEVICE_ID_NVIDIA_CK804_SLAVE        0x00d3
 #define PCI_DEVICE_ID_NVIDIA_ITNT2		0x00A0
 #define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR	0x0100
 #define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR	0x0101
@@ -919,23 +961,6 @@
 #define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2		0x0202
 #define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC		0x0203
 
-#define PCI_DEVICE_ID_NVIDIA_CK804_HT           0x005e
-#define PCI_DEVICE_ID_NVIDIA_CK804_LPC          0x0050
-#define PCI_DEVICE_ID_NVIDIA_CK804_PRO          0x0051
-#define PCI_DEVICE_ID_NVIDIA_CK804_SLAVE        0x00d3
-#define PCI_DEVICE_ID_NVIDIA_CK804_SM           0x0052
-#define PCI_DEVICE_ID_NVIDIA_CK804_ACPI         0x0052
-#define PCI_DEVICE_ID_NVIDIA_CK804_USB          0x005a
-#define PCI_DEVICE_ID_NVIDIA_CK804_USB2         0x005b
-#define PCI_DEVICE_ID_NVIDIA_CK804_NIC          0x0056
-#define PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE   0x0057
-#define PCI_DEVICE_ID_NVIDIA_CK804_ACI          0x0059
-#define PCI_DEVICE_ID_NVIDIA_CK804_MCI          0x0058
-#define PCI_DEVICE_ID_NVIDIA_CK804_IDE          0x0053
-#define PCI_DEVICE_ID_NVIDIA_CK804_SATA0        0x0054
-#define PCI_DEVICE_ID_NVIDIA_CK804_SATA1        0x0055
-#define PCI_DEVICE_ID_NVIDIA_CK804_PCI          0x005c
-#define PCI_DEVICE_ID_NVIDIA_CK804_PCI_E        0x005d
 
 #define PCI_VENDOR_ID_IMS		0x10e0
 #define PCI_DEVICE_ID_IMS_8849		0x8849
@@ -1812,7 +1837,9 @@
 #define PCI_DEVICE_ID_INTEL_6300ESB_USB2 0x25aa
 #define PCI_DEVICE_ID_INTEL_6300ESB_USB3 0x25ad
 #define PCI_DEVICE_ID_INTEL_6300ESB_SATA 0x25a3
+#define PCI_DEVICE_ID_INTEL_6300ESB_SATA_R 0x25b0
 #define PCI_DEVICE_ID_INTEL_6300ESB_PIC1 0x25ac
+#define PCI_DEVICE_ID_INTEL_6300ESB_BRIDGE1C 0x25ae
 #define PCI_DEVICE_ID_INTEL_80310	0x530d
 #define PCI_DEVICE_ID_INTEL_82810_MC1	0x7120
 #define PCI_DEVICE_ID_INTEL_82810_IG1	0x7121
diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h
new file mode 100644
index 0000000000..9ea662d490
--- /dev/null
+++ b/src/include/device/pciexp.h
@@ -0,0 +1,11 @@
+#ifndef DEVICE_PCIEXP_H
+#define DEVICE_PCIEXP_H
+/* (c) 2005 Linux Networx GPL see COPYING for details */
+
+unsigned int pciexp_scan_bus(struct bus *bus, 
+	unsigned min_devfn, unsigned max_devfn, unsigned int max);
+unsigned int pciexp_scan_bridge(device_t dev, unsigned int max);
+
+extern struct device_operations default_pciexp_ops_bus;
+
+#endif /* DEVICE_PCIEXP_H */
diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h
new file mode 100644
index 0000000000..8bf193530a
--- /dev/null
+++ b/src/include/device/pcix.h
@@ -0,0 +1,12 @@
+#ifndef DEVICE_PCIX_H
+#define DEVICE_PCIX_H
+/* (c) 2005 Linux Networx GPL see COPYING for details */
+
+unsigned int pcix_scan_bus(struct bus *bus, 
+	unsigned min_devfn, unsigned max_devfn, unsigned int max);
+unsigned int pcix_scan_bridge(device_t dev, unsigned int max);
+const char *pcix_speed(unsigned sstatus);
+
+extern struct device_operations default_pcix_ops_bus;
+
+#endif /* DEVICE_PCIX_H */
diff --git a/src/include/device/resource.h b/src/include/device/resource.h
index a5c7f0a31a..902cf686c9 100644
--- a/src/include/device/resource.h
+++ b/src/include/device/resource.h
@@ -98,4 +98,7 @@ extern void search_global_resources(
 	unsigned long type_mask, unsigned long type,
 	resource_search_t search, void *gp);
 
+#define RESOURCE_TYPE_MAX 20
+extern const char *resource_type(struct resource *resource);
+
 #endif /* RESOURCE_H */