diff options
| author | Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> | 2024-11-01 15:22:04 +0800 |
|---|---|---|
| committer | Yu-Ping Wu <yupingso@google.com> | 2024-11-21 13:47:09 +0000 |
| commit | 5f3a7d098ea0e70bcd1566b5d104438389c5d26c (patch) | |
| tree | 88bee51d26a3d0aad0113f4e8ab03aa062e6bc48 /src/include/device/pciexp.h | |
| parent | feddd37297d2157504540aa861e86e7e2aeba782 (diff) | |
mb/google/rauru: Initialize DPM in ramstage
Add initialization of DPM drvier for DRAM low power mode. This DPM flow
adds 3ms to the boot time, making the total boot time 860ms.
coreboot logs:
CBFS: Found 'dpm.dm' @0x19880 size 0x5b7 in mcache @0xfffdd1fc
mtk_init_mcu: Loaded (and reset) dpm.dm in 0 msecs (1888 bytes)
CBFS: Found 'dpm.pm' @0x19ec0 size 0x7fb5 in mcache @0xfffdd258
mtk_init_mcu: Loaded (and reset) dpm.pm in 3 msecs (43844 bytes)
TEST=Build pass. Check with cbmem -1.
BUG=b:317009620
Change-Id: Ib855e133a30067fc89c88d5c0fb454cc78504ff3
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85122
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device/pciexp.h')
0 files changed, 0 insertions, 0 deletions