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authorPatrick Rudolph <patrick.rudolph@9elements.com>2023-12-14 14:43:54 +0100
committerFelix Singer <service+coreboot-gerrit@felixsinger.de>2023-12-23 19:58:44 +0000
commit8ed0cd0acc788f37ebfd47980843f1f39efe2581 (patch)
tree3a781b282efb6283350dcf1bd195a0333935266f /src/include/device/pci_ids.h
parent893d77e3fe5bf02fdc25209ca675d6b31c288623 (diff)
sb/intel/bd82x6x: Add defines for PCI IDs
Add and use defines for 6 series and 7 series PCH PCH IDs. Change-Id: I4de37d5817766b9bc4f5c2d4d472d3c456b14b29 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79546 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device/pci_ids.h')
-rw-r--r--src/include/device/pci_ids.h44
1 files changed, 44 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index e2836c8cf8..ae749019ea 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2816,6 +2816,50 @@
#define PCI_DID_INTEL_IBEXPEAK_HECI1 0x3b64
#define PCI_DID_INTEL_IBEXPEAK_THERMAL 0x3b32
+/* Intel Mobile 6 Series Chipset and 7 Series Chipset */
+#define PCI_DID_INTEL_6_SERIES_MOBILE_SFF 0x1c41
+#define PCI_DID_INTEL_6_SERIES_MOBILE 0x1c43
+#define PCI_DID_INTEL_6_SERIES_UM67 0x1c47
+#define PCI_DID_INTEL_6_SERIES_HM65 0x1c49
+#define PCI_DID_INTEL_6_SERIES_HM67 0x1c4b
+#define PCI_DID_INTEL_6_SERIES_QS67 0x1c4d
+#define PCI_DID_INTEL_6_SERIES_QM67 0x1c4f
+
+#define PCI_DID_INTEL_7_SERIES_MOBILE 0x1e42
+#define PCI_DID_INTEL_7_SERIES_MOBILE_SFF 0x1e43
+#define PCI_DID_INTEL_7_SERIES_QM77 0x1e55
+#define PCI_DID_INTEL_7_SERIES_QS77 0x1e56
+#define PCI_DID_INTEL_7_SERIES_HM77 0x1e57
+#define PCI_DID_INTEL_7_SERIES_UM77 0x1e58
+#define PCI_DID_INTEL_7_SERIES_HM76 0x1e59
+#define PCI_DID_INTEL_7_SERIES_HM75 0x1e5d
+#define PCI_DID_INTEL_7_SERIES_HM70 0x1e5e
+#define PCI_DID_INTEL_7_SERIES_NM70 0x1e5f
+
+/* Intel Desktop/Server 6 Series Chipset and 7 Series Chipset */
+
+#define PCI_DID_INTEL_6_DESKTOP_SAMPLE 0x1c42
+#define PCI_DID_INTEL_6_SERIES_Z68 0x1c44
+#define PCI_DID_INTEL_6_SERIES_P67 0x1c46
+#define PCI_DID_INTEL_6_SERIES_H67 0x1c4a
+#define PCI_DID_INTEL_6_SERIES_Q65 0x1c4c
+#define PCI_DID_INTEL_6_SERIES_Q67 0x1c4e
+#define PCI_DID_INTEL_6_SERIES_B65 0x1c50
+#define PCI_DID_INTEL_6_SERIES_C202 0x1c52
+#define PCI_DID_INTEL_6_SERIES_C204 0x1c54
+#define PCI_DID_INTEL_6_SERIES_C206 0x1c56
+#define PCI_DID_INTEL_6_SERIES_H61 0x1c5c
+
+#define PCI_DID_INTEL_7_SERIES_DESKTOP_SAMPLE 0x1e41
+#define PCI_DID_INTEL_7_SERIES_Z77 0x1e44
+#define PCI_DID_INTEL_7_SERIES_H71 0x1e45
+#define PCI_DID_INTEL_7_SERIES_Z75 0x1e46
+#define PCI_DID_INTEL_7_SERIES_Q77 0x1e47
+#define PCI_DID_INTEL_7_SERIES_Q75 0x1e48
+#define PCI_DID_INTEL_7_SERIES_B75 0x1e49
+#define PCI_DID_INTEL_7_SERIES_H77 0x1e4a
+#define PCI_DID_INTEL_7_SERIES_C216 0x1e53
+
/* Intel SDMA device Ids */
#define PCI_DID_INTEL_LPT_LP_SDMA 0x9c60