diff options
| author | Gaggery Tsai <gaggery.tsai@intel.com> | 2019-12-05 11:23:20 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-13 09:05:20 +0000 |
| commit | 12a651c060963ed89b46db6b00195874419417ca (patch) | |
| tree | 1dfa70693d9f039b2be0101f280fcc34aeb5bf1d /src/include/device/pci_ids.h | |
| parent | d1613f5681f17c02e5219342a0edc39e4aed685d (diff) | |
soc/intel/common: Add PCI device IDs for CMP-H
This patch adds PCI device IDs for CMP-H.
TEST=build coreboot.rom and boot to the OS
Change-Id: Ia7413f75757c64b389a39d6e171f88eb61036c58
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/include/device/pci_ids.h')
| -rw-r--r-- | src/include/device/pci_ids.h | 49 |
1 files changed, 48 insertions, 1 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 43752f8368..bd5b3a5148 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2930,6 +2930,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14 0x9db5 #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15 0x9db6 #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16 0x9db7 + #define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP1 0x34b8 #define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP2 0x34b9 #define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP3 0x34ba @@ -3005,7 +3006,30 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14 0x02b5 #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15 0x02b6 #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16 0x02b7 - +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP1 0x06b8 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP2 0x06b9 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP3 0x06ba +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP4 0x06bb +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP5 0x06bc +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP6 0x06bd +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP7 0x06be +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP8 0x06bf +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP9 0x06b0 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP10 0x06b1 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP11 0x06b2 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP12 0x06b3 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP13 0x06b4 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP14 0x06b5 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP15 0x06b6 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP16 0x06b7 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP17 0x06c0 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP18 0x06c1 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP19 0x06c2 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP20 0x06c3 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP21 0x06ac +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP22 0x06ad +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP23 0x06ae +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP24 0x06af #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP1 0x38b8 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP2 0x38b9 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP3 0x38ba @@ -3042,6 +3066,9 @@ #define PCI_DEVICE_ID_INTEL_CMP_SATA 0x02d5 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA 0x02d7 #define PCI_DEVICE_ID_INTEL_CMP_LP_SATA 0x02d3 +#define PCI_DEVICE_ID_INTEL_CMP_H_SATA 0x06d2 +#define PCI_DEVICE_ID_INTEL_CMP_H_HALO_SATA 0x06d3 +#define PCI_DEVICE_ID_INTEL_CMP_H_PREMIUM_SATA 0x06d7 #define PCI_DEVICE_ID_INTEL_TGP_LP_SATA 0xa0d3 #define PCI_DEVICE_ID_INTEL_TGP_SATA 0xa0d5 #define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA 0xa0d7 @@ -3060,6 +3087,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_PMC 0xa321 #define PCI_DEVICE_ID_INTEL_ICP_PMC 0x34a1 #define PCI_DEVICE_ID_INTEL_CMP_PMC 0x02a1 +#define PCI_DEVICE_ID_INTEL_CMP_H_PMC 0x06a1 #define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC 0x38a1 @@ -3112,6 +3140,10 @@ #define PCI_DEVICE_ID_INTEL_CMP_I2C3 0x02eb #define PCI_DEVICE_ID_INTEL_CMP_I2C4 0x02c5 #define PCI_DEVICE_ID_INTEL_CMP_I2C5 0x02c6 +#define PCI_DEVICE_ID_INTEL_CMP_H_I2C0 0x06e8 +#define PCI_DEVICE_ID_INTEL_CMP_H_I2C1 0x06e9 +#define PCI_DEVICE_ID_INTEL_CMP_H_I2C2 0x06ea +#define PCI_DEVICE_ID_INTEL_CMP_H_I2C3 0x06eb #define PCI_DEVICE_ID_INTEL_TGP_I2C0 0xa0e8 #define PCI_DEVICE_ID_INTEL_TGP_I2C1 0xa0e9 #define PCI_DEVICE_ID_INTEL_TGP_I2C2 0xa0ea @@ -3158,6 +3190,9 @@ #define PCI_DEVICE_ID_INTEL_CMP_UART0 0x02a8 #define PCI_DEVICE_ID_INTEL_CMP_UART1 0x02a9 #define PCI_DEVICE_ID_INTEL_CMP_UART2 0x02c7 +#define PCI_DEVICE_ID_INTEL_CMP_H_UART0 0x06a8 +#define PCI_DEVICE_ID_INTEL_CMP_H_UART1 0x06a9 +#define PCI_DEVICE_ID_INTEL_CMP_H_UART2 0x06c7 #define PCI_DEVICE_ID_INTEL_TGP_UART0 0xa0a8 #define PCI_DEVICE_ID_INTEL_TGP_UART1 0xa0a9 #define PCI_DEVICE_ID_INTEL_TGP_UART2 0xa0c7 @@ -3195,6 +3230,10 @@ #define PCI_DEVICE_ID_INTEL_CMP_SPI1 0x02ab #define PCI_DEVICE_ID_INTEL_CMP_SPI2 0x02fb #define PCI_DEVICE_ID_INTEL_CMP_HWSEQ_SPI 0x02a4 +#define PCI_DEVICE_ID_INTEL_CMP_H_SPI0 0x06aa +#define PCI_DEVICE_ID_INTEL_CMP_H_SPI1 0x06ab +#define PCI_DEVICE_ID_INTEL_CMP_H_SPI2 0x06fb +#define PCI_DEVICE_ID_INTEL_CMP_H_HWSEQ_SPI 0x06a4 #define PCI_DEVICE_ID_INTEL_TGP_SPI0 0xa0a4 #define PCI_DEVICE_ID_INTEL_TGP_GSPI0 0xa0aa #define PCI_DEVICE_ID_INTEL_TGP_GSPI1 0xa0ab @@ -3379,6 +3418,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SMBUS 0xa323 #define PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS 0x34a3 #define PCI_DEVICE_ID_INTEL_CMP_SMBUS 0x02a3 +#define PCI_DEVICE_ID_INTEL_CMP_H_SMBUS 0x06a3 #define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS 0x38a3 @@ -3394,6 +3434,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_XHCI 0xa36d #define PCI_DEVICE_ID_INTEL_ICP_LP_XHCI 0x34ed #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed +#define PCI_DEVICE_ID_INTEL_CMP_H_XHCI 0x06ed #define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI 0x38ed @@ -3409,6 +3450,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_P2SB 0xa320 #define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0 #define PCI_DEVICE_ID_INTEL_CMP_P2SB 0x02a0 +#define PCI_DEVICE_ID_INTEL_CMP_H_P2SB 0x06a0 #define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB 0x38a0 @@ -3419,6 +3461,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SRAM 0xa36f #define PCI_DEVICE_ID_INTEL_ICL_SRAM 0x34ef #define PCI_DEVICE_ID_INTEL_CMP_SRAM 0x02ef +#define PCI_DEVICE_ID_INTEL_CMP_H_SRAM 0x06ef #define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM 0x38ef @@ -3434,6 +3477,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_AUDIO 0xa348 #define PCI_DEVICE_ID_INTEL_ICL_AUDIO 0x34c8 #define PCI_DEVICE_ID_INTEL_CMP_AUDIO 0x02c8 +#define PCI_DEVICE_ID_INTEL_CMP_H_AUDIO 0x06c8 #define PCI_DEVICE_ID_INTEL_BSW_AUDIO 0x2284 #define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO 0x38c8 @@ -3452,6 +3496,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_CSE0 0xa360 #define PCI_DEVICE_ID_INTEL_ICL_CSE0 0x34e0 #define PCI_DEVICE_ID_INTEL_CMP_CSE0 0x02e0 +#define PCI_DEVICE_ID_INTEL_CMP_H_CSE0 0x06e0 #define PCI_DEVICE_ID_INTEL_TGL_CSE0 0xa0e0 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0 0x38e0 @@ -3463,6 +3508,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_XDCI 0xa36e #define PCI_DEVICE_ID_INTEL_ICP_LP_XDCI 0x34ee #define PCI_DEVICE_ID_INTEL_CMP_LP_XDCI 0x02ee +#define PCI_DEVICE_ID_INTEL_CMP_H_XDCI 0x06ee #define PCI_DEVICE_ID_INTEL_TGP_LP_XDCI 0xa0ee /* Intel SD device Ids */ @@ -3473,6 +3519,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SD 0xa375 #define PCI_DEVICE_ID_INTEL_ICL_SD 0x34f8 #define PCI_DEVICE_ID_INTEL_CMP_SD 0x02f5 +#define PCI_DEVICE_ID_INTEL_CMP_H_SD 0x06f5 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD 0x38f8 /* Intel EMMC device Ids */ |