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author | Arthur Heymans <arthur@aheymans.xyz> | 2017-09-09 12:06:16 +0200 |
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committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-14 21:45:39 +0000 |
commit | 106a3e8c7a3e0aba9d6e5a9c171d0e999063951a (patch) | |
tree | 15e8027085e723316212baa0944a1c0e53117e95 /src/include/device/pci_ehci.h | |
parent | ffdd33c312cf5ea895c1dad522edb603801d4c37 (diff) |
mb/asrock/g41c-gs: Add IO decode range for SIO HWMON
Change-Id: Ic02c3a6265f11c1571369bc04371d28b6f989736
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21464
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device/pci_ehci.h')
0 files changed, 0 insertions, 0 deletions