diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2017-09-22 19:07:21 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-13 15:21:48 +0000 |
| commit | 2188f57a806feb7b25816d70919f12e5e2ba84b3 (patch) | |
| tree | a24b2c92ff1821c0b988f5f6dffe66a3a78190b7 /src/include/device/pci_def.h | |
| parent | c8374e32920d2bffbd5fe7b65621fe0b90cfb19e (diff) | |
src/device: Update LTR configuration scheme
This patch moves out LTR programming under L1 substate
to pchexp_tune_device function, as substate programming
and LTR programming are independent.
LTR programming scheme is updated to scan through entire
tree and enable LTR mechanism on pci device if LTR mechanism
is supported by device.
BRANCH=none
BUG=b:66722364
TEST=Verify LTR is configured for end point devices and max
snoop latency gets configured.
Change-Id: I6be99c3b590c1457adf88bc1b40f128fcade3fbe
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/21868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include/device/pci_def.h')
| -rw-r--r-- | src/include/device/pci_def.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 1674ee1e49..60d913204a 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -373,6 +373,12 @@ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ +#define PCI_EXP_DEV_CAP2_OFFSET 0x24 /* Device Capabilities 2 offset */ +/* LTR mechanism supported.Bit 11 of Device Cap 2 Register */ +#define LTR_MECHANISM_SUPPORT (1 << 11) +#define PCI_EXP_DEV_CTL_STS2_CAP_OFFSET 0x28 /* Device Control 2 offset */ +/* LTR mechanism enable. Bit 10 of Device Control 2 Register */ +#define LTR_MECHANISM_EN (1 << 10) #define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */ #define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ #define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ |