summaryrefslogtreecommitdiff
path: root/src/include/device/pci_def.h
diff options
context:
space:
mode:
authorYuchi Chen <yuchi.chen@intel.com>2024-06-25 11:08:12 +0800
committerLean Sheng Tan <sheng.tan@9elements.com>2024-11-09 10:19:28 +0000
commit031c078e8634c6436d27297e2b7810a5b75fc5b8 (patch)
treea0e9ad49c41e7f0634ea8b906bcea6d5fce85732 /src/include/device/pci_def.h
parent239f7f7408a1dca881b3b4294d0bbea7b4a8ed60 (diff)
include/device/pci_def.h: Add PCIe SRIOV definitions
Add SRIOV related definitions from section 9.3 of PCI Express Base Specification Revision 6.2. Change-Id: Ic4bf76b0e3b20e3d04e8264c6530ab4abb95a013 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Diffstat (limited to 'src/include/device/pci_def.h')
-rw-r--r--src/include/device/pci_def.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index 6d61e6d2bd..6748b356b7 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -478,6 +478,7 @@
#define PCIE_EXT_CAP_LTR_ID 0x0018
#define PCIE_EXT_CAP_RESIZABLE_BAR 0x0015
#define PCIE_EXT_CAP_RCECEA_ID 0x0007
+#define PCIE_EXT_CAP_SRIOV_ID 0x0010
/* Secondary PCI Express Extended Capability Structure */
#define PCI_EXP_SEC_CAP_ID 0x19
@@ -580,6 +581,16 @@
#define PCI_RCECEA_BUSNUM 8
/*
+ * Single Root IO Virtualization
+ * Section 9.3 of PCI Express Base Specification Revision 6.2.
+ */
+#define PCIE_EXT_CAP_SRIOV_TOTAL_VFS 0x0e
+#define PCIE_EXT_CAP_SRIOV_SUPPORTED_PAGE_SIZE 0x1c
+#define PCIE_EXT_CAP_SRIOV_SYSTEM_PAGE_SIZE 0x20
+#define PCIE_EXT_CAP_SRIOV_VF_BAR0 0x24
+#define PCIE_EXT_CAP_SRIOV_VF_BAR5 0x38
+
+/*
* The PCI interface treats multi-function devices as independent
* devices. The slot/function address of each device is encoded
* in a single byte as follows: