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authorSubrata Banik <subratabanik@google.com>2022-03-14 12:00:02 +0530
committerFelix Held <felix-coreboot@felixheld.de>2022-03-17 14:37:43 +0000
commit2f1f5ecf8a3dec193bbc1c33f88a1b3b34e4809f (patch)
tree2f5f425fec4e3f14031219d0047fa5e81d2bf750 /src/include/device/pci.h
parent9e4a38795c2392dee1d1043bb51d5af58bcb3a67 (diff)
soc/intel/common/block/p2sb: Refactor P2SB to add comprehend future SoC
This patch refactors the current P2SB common code driver to accommodate the future SoC platform with provision of more than one P2SB IP in disaggregated die architecture. IA SoC has only one P2SB in PCH die between SKL to ADL. Starting with MTL, one more P2SB IP resides in IOE die along with SoC die. (PCH die is renamed as SoC in MTL.) P2SB library (p2sblib.c) is common between PCH/SoC and IOE, and p2sb.c is added only for PCH/SoC P2SB. BUG=b:224325352 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib671d9acbfdc61305ebb401499bfc4742b738ffb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/include/device/pci.h')
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