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| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-09-22 15:42:08 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-12 15:33:26 +0000 |
| commit | 249bb8df0aa7f218c58199281495fc6fcbb45a8f (patch) | |
| tree | d39d11a1316046dadf0ca45ebde25b8062bd90ac /src/include/device/i2c_bus.h | |
| parent | 7a042229036c3dde2b443788389d6adfe1c1dd67 (diff) | |
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373
Update FSP headers for Tiger Lake platform generated based on FSP
version 3373. Previous version was 3333.
Changes include below UPDs:
ITbtPcieTunnelingForUsb4
SlowSlewRate
FastPkgCRampDisable
BUG=b:169759177
BRANCH=none
TEST=build and boot delbin/tglrvp
Cq-Depend:chrome-internal:3308203, chrome-internal:3308204
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45630
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device/i2c_bus.h')
0 files changed, 0 insertions, 0 deletions