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authorElyes HAOUAS <ehaouas@noos.fr>2020-08-19 21:51:55 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-09-14 07:09:41 +0000
commit563fc0889fcaee05d104f40d7f22fc27046bbe24 (patch)
tree1e39e353ed0d160e76b08b30abd4cc517d76891f /src/include/device/dram
parent7c79d8302b7361a11a204131d5661d768feb82ac (diff)
src/include: Drop unneeded empty lines
Change-Id: Ie325541547ea10946f41a8f979d144a06a7e80eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/include/device/dram')
-rw-r--r--src/include/device/dram/ddr3.h1
-rw-r--r--src/include/device/dram/ddr4.h1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index 74e0ff55f1..0814990eb9 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -19,7 +19,6 @@
#include <device/dram/common.h>
#include <types.h>
-
/**
* Convenience definitions for SPD offsets
*
diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h
index f258fa9f09..d22d4bc500 100644
--- a/src/include/device/dram/ddr4.h
+++ b/src/include/device/dram/ddr4.h
@@ -21,7 +21,6 @@
#define SPD_DDR4_PART_OFF 329
#define SPD_DDR4_PART_LEN 20
-
/*
* Module type (byte 3, bits 3:0) of SPD
* This definition is specific to DDR4. DDR2/3 SPDs have a different structure.