diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-06 18:01:04 -0800 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-09 17:16:09 +0100 |
| commit | 0ca2a0654ca4b403e8a54d558bce07a862820a9d (patch) | |
| tree | 86c845b441c8ae4824bf6178943148ec94441c6d /src/include/device/device.h | |
| parent | 75d8d8da47a3cc759d7395f5b0ef91ba13a59e51 (diff) | |
src/include: Fix unsigned warnings
Fix warning detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
BRANCH=none
BUG=None
TEST=Build and run on Galileo Gen2
Change-Id: I23d9b4b715aa74acc387db8fb8d3c73bd5cabfaa
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18607
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/include/device/device.h')
| -rw-r--r-- | src/include/device/device.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/include/device/device.h b/src/include/device/device.h index 284c039fc8..6fcb9ae8a4 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -85,7 +85,7 @@ struct bus { ROMSTAGE_CONST struct device * dev; /* This bridge device */ ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ - unsigned bridge_ctrl; /* Bridge control register */ + unsigned int bridge_ctrl; /* Bridge control register */ uint16_t bridge_cmd; /* Bridge command register */ unsigned char link_num; /* The index of this link */ uint16_t secondary; /* secondary bus number */ @@ -93,9 +93,9 @@ struct bus { unsigned char cap; /* PCi capability offset */ uint32_t hcdn_reg; /* For HyperTransport link */ - unsigned reset_needed : 1; - unsigned disable_relaxed_ordering : 1; - unsigned ht_link_up : 1; + unsigned int reset_needed : 1; + unsigned int disable_relaxed_ordering : 1; + unsigned int ht_link_up : 1; }; /* @@ -119,8 +119,8 @@ struct device { ROMSTAGE_CONST struct device * next; /* chain of all devices */ struct device_path path; - unsigned vendor; - unsigned device; + unsigned int vendor; + unsigned int device; u16 subsystem_vendor; u16 subsystem_device; unsigned int class; /* 3 bytes: (base, sub, prog-if) */ @@ -201,11 +201,11 @@ device_t dev_find_path(device_t prev_match, enum device_path_type path_type); device_t dev_find_slot (unsigned int bus, unsigned int devfn); device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); device_t dev_find_slot_pnp(u16 port, u16 device); -device_t dev_find_lapic(unsigned apic_id); +device_t dev_find_lapic(unsigned int apic_id); int dev_count_cpu(void); -device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled); -void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned core, unsigned thread); +device_t add_cpu_device(struct bus *cpu_bus, unsigned int apic_id, int enabled); +void set_cpu_topology(device_t cpu, unsigned int node, unsigned int package, unsigned int core, unsigned int thread); #define amd_cpu_topology(cpu, node, core) \ set_cpu_topology(cpu, node, 0, core, 0) |