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author | Angel Pons <th3fanbus@gmail.com> | 2020-11-14 16:18:15 +0100 |
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committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-20 00:34:17 +0000 |
commit | 3d3bf484f549fba6a1256150b2ae857fe8d19fba (patch) | |
tree | d3c5420a1e03c6b6d4045bb429bc2bfc2e67c3c7 /src/include/delay.h | |
parent | cf5dd49d3c9a513d379c0210fa7c7a6f5c52ff36 (diff) |
nb/intel/sandybridge: Introduce `ddr3_mirror_mrreg` helper
Write training needs to update mode register 1, but `write_mrreg` will
clobber the IOSAV sequence. Reference code uses one four-subsequence to
unset Qoff in MR1, run the test, and finally set Qoff again. This will
be implemented in future changes, and will use the newly-added helper.
Change-Id: I06a06a7bdd43dbde34af4ea2f90e00873eefe599
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/include/delay.h')
0 files changed, 0 insertions, 0 deletions