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| author | derek.huang <derek.huang@intel.corp-partner.google.com> | 2020-04-23 14:55:24 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-06 08:48:24 +0000 |
| commit | e685107dd61461f91d3fdbf722cf378e121e2551 (patch) | |
| tree | 6dca5dff27e49b7ef52f1b3f296610fbd13ad492 /src/include/cpu | |
| parent | 18e632f8b33b8c764db124e65b9ccab16044f108 (diff) | |
soc/intel/tigerlake: Print HPR_CAUSE0 register
In addition to GBLRST_CAUSE0 and GBLRST_CAUSE1, print the value
of HPR_CAUSE0.
Change-Id: Idc57c3cd6a8d156c5544640898e8e7147d34c535
Signed-off-by: derek.huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/include/cpu')
0 files changed, 0 insertions, 0 deletions