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authorKerry Sheh <shekairui@gmail.com>2012-02-07 20:31:35 +0800
committerMarc Jones <marcj303@gmail.com>2012-02-16 19:26:32 +0100
commitd3e990c6e5124f30b394f5dbd4902ea8bf341b07 (patch)
treec5667f18c6b406a0350e43db4f760ca97174f98d /src/include/cpu
parent53c1d204ed134017e9a04d68f175bb7f6c6e0915 (diff)
AGESA F15: AGESA family15 model 00-0fh cpu wrapper
Change-Id: I7580bc063c09d99d3fca8b20cd39df2384a6ad44 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/555 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/include/cpu')
-rw-r--r--src/include/cpu/amd/amdfam15.h41
1 files changed, 41 insertions, 0 deletions
diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h
new file mode 100644
index 0000000000..3d300de511
--- /dev/null
+++ b/src/include/cpu/amd/amdfam15.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_AMD_FAM15_H
+#define CPU_AMD_FAM15_H
+
+#include <cpu/x86/msr.h>
+
+#define MCI_STATUS 0x00000401
+#define HWCR_MSR 0xC0010015
+#define NB_CFG_MSR 0xC001001f
+
+#define LS_CFG_MSR 0xC0011020
+#define IC_CFG_MSR 0xC0011021
+#define DC_CFG_MSR 0xC0011022
+#define CU_CFG_MSR 0xC0011023
+#define CU_CFG2_MSR 0xC001102A
+
+#define CPU_ID_FEATURES_MSR 0xC0011004
+#define CPU_ID_EXT_FEATURES_MSR 0xC0011005
+
+static msr_t rdmsr_amd(u32 index);
+static void wrmsr_amd(u32 index, msr_t msr);
+
+#endif /* CPU_AMD_FAM15_H */