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authorFelix Held <felix-coreboot@felixheld.de>2021-07-13 18:31:40 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-07-14 17:35:17 +0000
commit71b918d882738fd99f7894d43a96d5782ad1928b (patch)
treecb5b0c3ab1961b4c041b0cd68a2a657d74b9f81c /src/include/cpu
parent4f51c94099b5a8308c0342830e1bf52f1ac095e9 (diff)
include/cpu/amd/msr: add and use MC_CTL_MASK macro
Add this macro to be able to conveniently access the MC_CTL_MASK register for each MCA bank. Also drop the unused definitions for MC1_CTL_MASK and MC4_CTL_MASK. Change-Id: I23ce1eac2ffce35a2b45387ee86aa77b52da5494 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/include/cpu')
-rw-r--r--src/include/cpu/amd/msr.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h
index 9edea5a06b..55a7841e7e 100644
--- a/src/include/cpu/amd/msr.h
+++ b/src/include/cpu/amd/msr.h
@@ -19,8 +19,7 @@
#define NB_CFG_MSR 0xC001001f
#define FidVidStatus 0xC0010042
#define MC0_CTL_MASK 0xC0010044
-#define MC1_CTL_MASK 0xC0010045
-#define MC4_CTL_MASK 0xC0010048
+#define MC_CTL_MASK(bank) (MC0_CTL_MASK + (bank))
#define MSR_INTPEND 0xC0010055
#define MMIO_CONF_BASE 0xC0010058
#define MMIO_RANGE_EN (1 << 0)