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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-05-25 08:52:07 +0300 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-06-15 18:34:45 +0000 |
| commit | 49c44cdccb936bf1179402b5927a1f477ad4e752 (patch) | |
| tree | c0bf42d989c20188fc9bac8b6bfd3c5ab99cf00b /src/include/cpu | |
| parent | c36469e0b12f41b624eea072014b715b3c564513 (diff) | |
arch/x86: Remove XIP_ROM_SIZE
When adding XIP stages on x86, the -P parameter was used to
pass a page size that covers the entire file to add. The same
can now be achieved with --pow2page and we no longer need to
define a static Konfig for the purpose.
TEST: Build asus/p2b and lenovo/x60 with "--pow2page -v -v" and
inspect the generated make.log files. The effective pagesize is
reduced from 64kB to 16kB for asus/p2b giving more freedom
for the stage placement inside CBFS. Pagesize remained at 64kB
for lenovo/x60.
Change-Id: I5891fa2c2bb2d44077f745619162b143d083a6d1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include/cpu')
| -rw-r--r-- | src/include/cpu/x86/mtrr.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 412330449f..9227710596 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -190,10 +190,6 @@ static inline unsigned int fls(unsigned int x) */ #define CACHE_TMP_RAMTOP (16<<20) -#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) -# error "CONFIG_XIP_ROM_SIZE is not a power of 2" -#endif - /* For ROM caching, generally, try to use the next power of 2. */ #define OPTIMAL_CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE) #define OPTIMAL_CACHE_ROM_BASE _FROM_4G_TOP(OPTIMAL_CACHE_ROM_SIZE) |