summaryrefslogtreecommitdiff
path: root/src/include/cpu
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-17 20:51:08 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-26 21:08:41 +0000
commitcd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf (patch)
treeb0438431df0943ab5f0fa9d80a99fc265130ac23 /src/include/cpu
parent16248e89ecf73a76e5d9e9e2de46146f7ffece88 (diff)
soc/intel: Use common romstage code
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/cpu')
-rw-r--r--src/include/cpu/intel/romstage.h14
1 files changed, 0 insertions, 14 deletions
diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h
deleted file mode 100644
index fd5d7f4e85..0000000000
--- a/src/include/cpu/intel/romstage.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef _CPU_INTEL_ROMSTAGE_H
-#define _CPU_INTEL_ROMSTAGE_H
-
-#include <arch/romstage.h>
-
-void mainboard_romstage_entry(void);
-
-/* fill_postcar_frame() is called after raminit completes and right before
- * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr()
- * to tag memory ranges as cacheable to speed up execution of postcar and
- * early ramstage. */
-void fill_postcar_frame(struct postcar_frame *pcf);
-
-#endif /* _CPU_INTEL_ROMSTAGE_H */