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authorLee Leahy <leroy.p.leahy@intel.com>2017-03-07 14:20:56 -0800
committerLee Leahy <leroy.p.leahy@intel.com>2017-03-10 22:29:01 +0100
commitf3d07f274e5084bf6958b0fbcbd3cb2bfd2c998e (patch)
tree0d5c8036aec01f249243815d5992252cdd2f1650 /src/include/cpu
parentf00e446e746da54b7cf967deae73cf090f3835eb (diff)
src/include: Add space after +
Fix the following error detected by checkpatch.pl: ERROR: need consistent spacing around '+' (ctx:WxV) Test: Build and run on Galileo Gen2 Change-Id: Idd5f2a6d8a3c8db9c1a127ed75cec589929832e3 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18650 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include/cpu')
-rw-r--r--src/include/cpu/amd/gx2def.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h
index 60db369cf3..2904857126 100644
--- a/src/include/cpu/amd/gx2def.h
+++ b/src/include/cpu/amd/gx2def.h
@@ -288,7 +288,7 @@
#define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F)
-#define GLCP_SYS_RSTPLL (MSR_GLCP +0x14 /* R/W */)
+#define GLCP_SYS_RSTPLL (MSR_GLCP + 0x14 /* R/W */)
#define RSTPLL_UPPER_MDIV_SHIFT 9
#define RSTPLL_UPPER_VDIV_SHIFT 6
#define RSTPLL_UPPER_FBDIV_SHIFT 0