diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-25 13:02:22 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2021-06-21 08:26:41 +0000 |
| commit | 232222727d51f2d254121738b2e3ff92b8c1dc1f (patch) | |
| tree | bf8be8f510686c774581c8afa6df0dfb6cc1a391 /src/include/cpu | |
| parent | d21b463fb058deccef3a2c2ad80d771b5aba9f19 (diff) | |
soc/intel/common: Add InSMM.STS support
Tested on HP 280 G2, SMMSTORE v1 and v2 still work.
Other tests:
- If one does not set BIOS_CONTROL bit WPD, SMMSTORE breaks.
- If one does not write the magic MSR `or 1`, SMMSTORE breaks.
Change-Id: Ia90c0e3f8ccf895bfb6d46ffe26750393dab95fb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/include/cpu')
| -rw-r--r-- | src/include/cpu/intel/msr.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index 097ddb6e27..6b2db88961 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -26,6 +26,8 @@ #define AESNI_DISABLE (1 << 1) #define AESNI_LOCK (1 << 0) +#define MSR_SPCL_CHIPSET_USAGE 0x1fe + #define MSR_PKG_C10_RESIDENCY 0x632 #endif /* CPU_INTEL_MSR_H */ |