diff options
| author | Yuchen He <yuchenhe126@gmail.com> | 2023-07-25 21:28:36 +0200 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-08-05 16:04:46 +0000 |
| commit | 1e67adbc73e30be098ce163e3d27a7a7ecf68ae0 (patch) | |
| tree | a2880851ac6c754d94fc056472beb5ec133ab0b4 /src/include/cpu | |
| parent | 71b8ee0da407158d51eb7d86a6e1d4c458fc8e96 (diff) | |
src/*/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
header="src/soc/amd/common/block/include/amdblocks/post_codes.h \
src/include/cpu/intel/post_codes.h \
src/soc/intel/common/block/include/intelblocks/post_codes.h"
array=`grep -r "#define POST_" $header | \
tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2`
for str in $array; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r $str src | cut -d ':' -f 1 | \
xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g"
done
Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad
Signed-off-by: Yuchen He <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/include/cpu')
| -rw-r--r-- | src/include/cpu/intel/post_codes.h | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/src/include/cpu/intel/post_codes.h b/src/include/cpu/intel/post_codes.h index 6c1ca79f20..adca9167ad 100644 --- a/src/include/cpu/intel/post_codes.h +++ b/src/include/cpu/intel/post_codes.h @@ -3,26 +3,26 @@ #ifndef CPU_INTEL_CAR_POST_CODES_H #define CPU_INTEL_CAR_POST_CODES_H -#define POST_SOC_SET_DEF_MTRR_TYPE 0x21 -#define POST_SOC_CLEAR_FIXED_MTRRS 0x22 // Intentional Duplicate -#define POST_SOC_DETERMINE_CPU_ADDR_BITS 0x22 -#define POST_SOC_BSP_INIT 0x23 -#define POST_SOC_COUNT_CORES 0x24 -#define POST_SOC_CPU_HYPER_THREADING 0x25 -#define POST_SOC_CPU_SIBLING_DELAY 0x26 -#define POST_SOC_CPU_AP_INIT 0x27 -#define POST_SOC_SET_MTRR_BASE 0x28 -#define POST_SOC_SET_MTRR_MASK 0x29 // Intentional Duplicate -#define POST_SOC_AP_HALT 0x29 -#define POST_SOC_SET_CAR_BASE 0x2a -#define POST_SOC_ENABLE_MTRRS 0x2b -#define POST_SOC_ENABLE_CACHE 0x2c -#define POST_SOC_DISABLE_CACHE 0x2d -#define POST_SOC_FILL_CACHE 0x2e -#define POST_BOOTBLOCK_BEFORE_C_ENTRY 0x2f +#define POSTCODE_SOC_SET_DEF_MTRR_TYPE 0x21 +#define POSTCODE_SOC_CLEAR_FIXED_MTRRS 0x22 // Intentional Duplicate +#define POSTCODE_SOC_DETERMINE_CPU_ADDR_BITS 0x22 +#define POSTCODE_SOC_BSP_INIT 0x23 +#define POSTCODE_SOC_COUNT_CORES 0x24 +#define POSTCODE_SOC_CPU_HYPER_THREADING 0x25 +#define POSTCODE_SOC_CPU_SIBLING_DELAY 0x26 +#define POSTCODE_SOC_CPU_AP_INIT 0x27 +#define POSTCODE_SOC_SET_MTRR_BASE 0x28 +#define POSTCODE_SOC_SET_MTRR_MASK 0x29 // Intentional Duplicate +#define POSTCODE_SOC_AP_HALT 0x29 +#define POSTCODE_SOC_SET_CAR_BASE 0x2a +#define POSTCODE_SOC_ENABLE_MTRRS 0x2b +#define POSTCODE_SOC_ENABLE_CACHE 0x2c +#define POSTCODE_SOC_DISABLE_CACHE 0x2d +#define POSTCODE_SOC_FILL_CACHE 0x2e +#define POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY 0x2f -#define POST_POSTCAR_DISABLE_CACHE 0x30 -#define POST_POSTCAR_DISABLE_DEF_MTRR 0x31 -#define POST_POSTCAR_TEARDOWN_DONE 0x32 +#define POSTCODE_POSTCAR_DISABLE_CACHE 0x30 +#define POSTCODE_POSTCAR_DISABLE_DEF_MTRR 0x31 +#define POSTCODE_POSTCAR_TEARDOWN_DONE 0x32 #endif |