Split the two usages of __ROMCC__:

__ROMCC__ now means "Don't use prototypes, since romcc doesn't support them."
__PRE_RAM__ means "Use simpler versions of functions, and no device tree."

There are probably some places where both are tested, but only one is needed.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

9 files changed, 12 insertions, 12 deletions

diff --git a/src/include/cpu/amd/dualcore.h b/src/include/cpu/amd/dualcore.h
index fb53c92909..1d33840668 100644
--- a/src/include/cpu/amd/dualcore.h
+++ b/src/include/cpu/amd/dualcore.h
@@ -15,7 +15,7 @@ struct node_core_id {
 struct node_core_id get_node_core_id(unsigned int nb_cfg_54);
 #endif
 
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
 struct device;
 unsigned get_apicid_base(unsigned ioapic_num);
 void amd_sibling_init(struct device *cpu);
diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h
index a3f3033b28..c2d59a62de 100644
--- a/src/include/cpu/amd/model_fxx_rev.h
+++ b/src/include/cpu/amd/model_fxx_rev.h
@@ -49,7 +49,7 @@ static inline int is_cpu_e0(void)
 }
 
 
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 static int is_e0_later_in_bsp(int nodeid)
 {
         uint32_t val;
@@ -96,7 +96,7 @@ static inline int is_cpu_pre_f2(void)
         return (cpuid_eax(1) & 0xfff0f) <  0x40f02;
 }
 
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 //AMD_F0_SUPPORT
 static int is_cpu_f0_in_bsp(int nodeid)
 {
diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h
index 2b7017d897..d86655dcdd 100644
--- a/src/include/cpu/amd/mtrr.h
+++ b/src/include/cpu/amd/mtrr.h
@@ -31,7 +31,7 @@
 #define TOP_MEM_MASK			0x007fffff
 #define TOP_MEM_MASK_KB			(TOP_MEM_MASK >> 10)
 
-#if !defined( __ROMCC__ ) && !defined (ASSEMBLY)
+#if !defined( __ROMCC__ ) && !defined (ASSEMBLY) && !defined(__PRE_RAM__)
 void amd_setup_mtrrs(void);
 #endif /* __ROMCC__ */
 
diff --git a/src/include/cpu/amd/quadcore.h b/src/include/cpu/amd/quadcore.h
index 54a1c9be22..f7b2d09a19 100644
--- a/src/include/cpu/amd/quadcore.h
+++ b/src/include/cpu/amd/quadcore.h
@@ -34,7 +34,7 @@ struct node_core_id {
 struct node_core_id get_node_core_id(u32 nb_cfg_54);
 #endif
 
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
 struct device;
 u32 get_apicid_base(u32 ioapic_num);
 void amd_sibling_init(struct device *cpu);
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
index af7d3d52ef..22bd1e7e47 100644
--- a/src/include/cpu/x86/cache.h
+++ b/src/include/cpu/x86/cache.h
@@ -41,7 +41,7 @@ static inline void disable_cache(void)
 	wbinvd();
 }
 
-#if !defined( __ROMCC__)  && defined (__GNUC__)
+#if !defined( __ROMCC__) && !defined(__PRE_RAM__) && defined (__GNUC__)
 void x86_enable_cache(void);
 #endif /* !__ROMCC__ */
 
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 9f2191940a..2b77177bbf 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -68,7 +68,7 @@ static inline __attribute__((always_inline)) void stop_this_cpu(void)
 }
 #endif
 
-#if ! defined (__ROMCC__)
+#if ! defined (__ROMCC__) && !defined(__PRE_RAM__)
 
 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
 
@@ -157,6 +157,6 @@ int start_cpu(struct device *cpu);
 #endif /* CONFIG_SMP */
 
 
-#endif /* !__ROMCC__ */
+#endif /* !__ROMCC__ && !__PRE_RAM__ */
 
 #endif /* CPU_X86_LAPIC_H */
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index c4bc55a343..69b4d8e78a 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -1,7 +1,7 @@
 #ifndef CPU_X86_MSR_H
 #define CPU_X86_MSR_H
 
-#if defined( __ROMCC__) && !defined (__GNUC__)
+#if defined( __ROMCC__)
 
 typedef __builtin_msr_t msr_t;
 
@@ -43,7 +43,7 @@ static inline void wrmsr(unsigned index, msr_t msr)
 		);
 }
 
-#endif /* ROMCC__ && !__GNUC__ */
+#endif /* __ROMCC__ */
 
 
 #endif /* CPU_X86_MSR_H */
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 704a9d4bb1..2243fe3080 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -32,7 +32,7 @@
 #define MTRRfix4K_F8000_MSR 0x26f
 
 
-#if !defined(__ROMCC__) && !defined (ASSEMBLY)
+#if !defined(__ROMCC__) && !defined (ASSEMBLY) && !defined(__PRE_RAM__)
 
 #include <device/device.h>
 
diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h
index 455cd239fe..9370adfe00 100644
--- a/src/include/cpu/x86/tsc.h
+++ b/src/include/cpu/x86/tsc.h
@@ -17,7 +17,7 @@ static tsc_t rdtsc(void)
 	return res;
 }
 
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined (__PRE_RAM__)
 static inline unsigned long long rdtscll(void)
 {
 	unsigned long long val;