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authorStefan Reinauer <stepan@coresystems.de>2010-03-28 21:26:54 +0000
committerStefan Reinauer <stepan@openbios.org>2010-03-28 21:26:54 +0000
commit35b6bbb7217956fe29f5d7f29d3ce780f1e640f5 (patch)
treedf9e6309e10de7887d8346c8e1fd2dcc2b1f3e2e /src/include/cpu/x86
parent83a1dd850b9f61929a2db17a9429d3d193e34bfb (diff)
drop unneeded __ROMCC__ checks when the check for __PRE_RAM__ is more
appropriate. Also, factor out post_code() for __PRE_RAM__ code and drop it from some mainboards. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include/cpu/x86')
-rw-r--r--src/include/cpu/x86/cache.h4
-rw-r--r--src/include/cpu/x86/lapic.h8
-rw-r--r--src/include/cpu/x86/msr.h3
-rw-r--r--src/include/cpu/x86/mtrr.h7
-rw-r--r--src/include/cpu/x86/tsc.h3
5 files changed, 9 insertions, 16 deletions
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
index 22bd1e7e47..55d39382db 100644
--- a/src/include/cpu/x86/cache.h
+++ b/src/include/cpu/x86/cache.h
@@ -41,8 +41,8 @@ static inline void disable_cache(void)
wbinvd();
}
-#if !defined( __ROMCC__) && !defined(__PRE_RAM__) && defined (__GNUC__)
+#if !defined(__PRE_RAM__)
void x86_enable_cache(void);
-#endif /* !__ROMCC__ */
+#endif
#endif /* CPU_X86_CACHE */
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index de99deebfe..8b44a6cb66 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -69,7 +69,7 @@ static inline __attribute__((always_inline)) void stop_this_cpu(void)
void stop_this_cpu(void);
#endif
-#if ! defined (__ROMCC__) && !defined(__PRE_RAM__)
+#if !defined(__PRE_RAM__)
#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
@@ -106,7 +106,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
return x;
}
-
static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
{
xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg), v);
@@ -150,14 +149,11 @@ static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
void setup_lapic(void);
-
#if CONFIG_SMP == 1
struct device;
int start_cpu(struct device *cpu);
-
#endif /* CONFIG_SMP */
-
-#endif /* !__ROMCC__ && !__PRE_RAM__ */
+#endif /* !__PRE_RAM__ */
#endif /* CPU_X86_LAPIC_H */
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 69b4d8e78a..cbbd5cfd85 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -1,7 +1,7 @@
#ifndef CPU_X86_MSR_H
#define CPU_X86_MSR_H
-#if defined( __ROMCC__)
+#if defined(__ROMCC__)
typedef __builtin_msr_t msr_t;
@@ -45,5 +45,4 @@ static inline void wrmsr(unsigned index, msr_t msr)
#endif /* __ROMCC__ */
-
#endif /* CPU_X86_MSR_H */
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 2243fe3080..2da2beefc9 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -32,18 +32,15 @@
#define MTRRfix4K_F8000_MSR 0x26f
-#if !defined(__ROMCC__) && !defined (ASSEMBLY) && !defined(__PRE_RAM__)
-
+#if !defined (ASSEMBLY) && !defined(__PRE_RAM__)
#include <device/device.h>
-
void enable_fixed_mtrr(void);
void x86_setup_var_mtrrs(unsigned address_bits);
void x86_setup_mtrrs(unsigned address_bits);
int x86_mtrr_check(void);
void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res);
void x86_setup_fixed_mtrrs(void);
-
-#endif /* __ROMCC__ */
+#endif
#endif /* CPU_X86_MTRR_H */
diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h
index 5531993f7d..c57362755a 100644
--- a/src/include/cpu/x86/tsc.h
+++ b/src/include/cpu/x86/tsc.h
@@ -17,7 +17,8 @@ static inline tsc_t rdtsc(void)
return res;
}
-#if !defined( __ROMCC__ ) && !defined (__PRE_RAM__)
+#if !defined(__ROMCC__)
+/* Too many registers for ROMCC */
static inline unsigned long long rdtscll(void)
{
unsigned long long val;