diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2018-04-18 01:00:27 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-25 15:32:56 +0000 |
| commit | 0f35af8f4293d004d634c24fe029287b598326e9 (patch) | |
| tree | 0ebd81f209a967a73b7be37ea6b21d5e5b5cc207 /src/include/cpu/x86 | |
| parent | cfb1680a88fb0a869ad7cb7dfccf27120af98d15 (diff) | |
arch/x86: add support for cache-as-ram paging
Processors, such as glk, need to have paging enabled while
in cache-as-ram mode because the front end is agressive about
fetching lines into the L1I cache. If the line is dirty and in
the L1D then it writes it back to "memory". However, in this case
there is no backing store so the cache-as-ram data that was written
back transforms to all 0xff's when read back in causing corruption.
In order to mitigate the failure add x86 architecture support for
enabling paging while in cache-as-ram mode. A Kconfig variable,
NUM_CAR_PAGE_TABLE_PAGES, determines the number of pages to carve
out for page tables within the cache-as-ram region. Additionally,
the page directory pointer table is also carved out of cache-as-ram.
Both areas are allocated from the persist-across-stages region
of cache-as-ram so all stages utilizing cache-as-ram don't corrupt
the page tables.
The two paging-related areas are loaded by calling
paging_enable_for_car() with the names of cbfs files to load the
initial paging structures from.
BUG=b:72728953
Change-Id: I7ea6e3e7be94a0ef9fd3205ce848e539bfbdcb6e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Diffstat (limited to 'src/include/cpu/x86')
| -rw-r--r-- | src/include/cpu/x86/pae.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h index 96999bb0a8..a8b5e893fc 100644 --- a/src/include/cpu/x86/pae.h +++ b/src/include/cpu/x86/pae.h @@ -27,6 +27,11 @@ void paging_set_pat(uint64_t pat); /* Set coreboot default PAT value. */ void paging_set_default_pat(void); +/* Load page directory pointer table and page tables from cbfs identified by + * the provided the names then enable paging. Return 0 on success, < 0 on + * failure. */ +int paging_enable_for_car(const char *pdpt_name, const char *pt_name); + #define MAPPING_ERROR ((void *)0xffffffffUL) void *map_2M_page(unsigned long page); |