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authorFelix Held <felix-coreboot@felixheld.de>2021-07-13 00:54:32 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-07-14 02:24:39 +0000
commit1b46e76df9ef0a4b38d782732ee914ab70667bfa (patch)
tree83b3471f79037cc7376e2817ddd2905922d4f7eb /src/include/cpu/x86
parente3f7ef22864402e72e1fa6c1df3bc79199c40bdc (diff)
include/cpu/x86/msr: introduce IA32_MC_*(x) macros
When accessing the MCA MSRs, the MCA bank number gets multiplied by 4 and added to the IA32_MC0_* define to get the MSR number. Add a macro that already does this calculation to avoid open coding this repeatedly. Change-Id: I2de753b8c8ac8dcff5a94d5bba43aa13bbf94b99 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56243 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/cpu/x86')
-rw-r--r--src/include/cpu/x86/msr.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index da1932cb66..dd969d765d 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -56,7 +56,9 @@
#define DCA_TYPE0_EN (1 << 0)
#define IA32_PAT 0x277
#define IA32_MC0_CTL 0x400
+#define IA32_MC_CTL(bank) (IA32_MC0_CTL + 4 * (bank))
#define IA32_MC0_STATUS 0x401
+#define IA32_MC_STATUS(bank) (IA32_MC0_STATUS + 4 * (bank))
#define MCA_STATUS_HI_VAL (1UL << (63 - 32))
#define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32))
#define MCA_STATUS_HI_UC (1UL << (61 - 32))
@@ -75,7 +77,9 @@
#define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH)
#define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0)
#define IA32_MC0_ADDR 0x402
+#define IA32_MC_ADDR(bank) (IA32_MC0_ADDR + 4 * (bank))
#define IA32_MC0_MISC 0x403
+#define IA32_MC_MISC(bank) (IA32_MC0_MISC + 4 * (bank))
#define IA32_VMX_BASIC_MSR 0x480
#define VMX_BASIC_HI_DUAL_MONITOR (1UL << (49 - 32))
#define IA32_VMX_MISC_MSR 0x485