diff options
| author | Eugene Myers <edmyers@tycho.nsa.gov> | 2020-02-12 13:31:30 -0500 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-02-21 09:01:57 +0000 |
| commit | 5544f62746aeb8e5e1a7916d9b509f4d9339f387 (patch) | |
| tree | 72d73bb846cb420e0ada71cab88de20d9eed0caf /src/include/cpu/x86/msr.h | |
| parent | 2b6d249632980ddf2162cc6f4530045214f5ba81 (diff) | |
security/intel/stm: Check for processor STM support
Check to ensure that dual monitor mode is supported on the
current processor. Dual monitor mode is normally supported on
any Intel x86 processor that has VTx support. The STM is
a hypervisor that executes in SMM dual monitor mode. This
check should fail only in the rare case were dual monitor mode
is disabled. If the check fails, then the STM will not
be initialized by coreboot.
Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Change-Id: I518bb2aa1bdec94b5b6d5e991d7575257f3dc6e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/include/cpu/x86/msr.h')
| -rw-r--r-- | src/include/cpu/x86/msr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 49abd41c00..c761bc04b6 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -74,6 +74,7 @@ #define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH) #define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0) #define IA32_VMX_BASIC_MSR 0x480 +#define VMX_BASIC_HI_DUAL_MONITOR (1UL << (49 - 32)) #define IA32_VMX_MISC_MSR 0x485 #define MC0_ADDR 0x402 #define MC0_MISC 0x403 |