diff options
| author | Lin Huang <hl@rock-chips.com> | 2016-06-16 10:39:10 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-23 17:26:00 +0200 |
| commit | 203fe7278ae2521edcaeda96740bcc5ffa36cbdd (patch) | |
| tree | 7b65737a6cd70e0b2ff32c18ffd3aad2ba713cd5 /src/include/cpu/x86/gdt.h | |
| parent | 321a6a94f974257a96e753dc013be58d69938e05 (diff) | |
rockchip/rk3399: correct sdram inc file DENALI_CTL_217_DATA value
for per cs training, there should be more cycles to switch delay line.
so increase W2W_DIFFCS_DLY_F0 value from 0x1 to 0x5.
BRANCH=none
BUG=chrome-os-partner:54144
TEST=run "stressapptest -M 1024 -s 1000" and pass
Change-Id: I11720b7c6f009789b88ca26fc5da88597ed1622e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 9de93beae09174d50a31d2df655529f71628f77c
Original-Change-Id: Ide23fff04fd63fb0afc538b610b7685756f79f8d
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/352953
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/15307
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/include/cpu/x86/gdt.h')
0 files changed, 0 insertions, 0 deletions