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authorarch import user (historical) <svn@openbios.org>2005-07-06 17:17:25 +0000
committerarch import user (historical) <svn@openbios.org>2005-07-06 17:17:25 +0000
commit6ca7636c8f52560e732cdd5b1c7829cda5aa2bde (patch)
treecc45ae7c4dea6e2c5338f52b4314106bf07023be /src/include/cpu/x86/bist.h
parentb2ed53dd5669c2c3839633bd2b3b4af709a5b149 (diff)
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51
Creator: Yinghai Lu <yhlu@tyan.com> cache_as_ram for AMD and some intel git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include/cpu/x86/bist.h')
-rw-r--r--src/include/cpu/x86/bist.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/include/cpu/x86/bist.h b/src/include/cpu/x86/bist.h
index 6a62150c68..ff66eabe9b 100644
--- a/src/include/cpu/x86/bist.h
+++ b/src/include/cpu/x86/bist.h
@@ -4,9 +4,14 @@
static void report_bist_failure(unsigned long bist)
{
if (bist != 0) {
+#if CONFIG_USE_INIT
+ printk_emerg("BIST failed: %08x", bist);
+#else
print_emerg("BIST failed: ");
print_emerg_hex32(bist);
+#endif
die("\r\n");
+
}
}