diff options
| author | Martin Roth <gaumless@gmail.com> | 2022-12-31 18:27:22 -0700 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2023-02-07 10:53:34 +0000 |
| commit | 0d34a50a360228138ade623e799b03eaba83b0a5 (patch) | |
| tree | f7091f1c391332e86cd2d9da9e84c40153d95c65 /src/include/cpu/intel | |
| parent | a891f71ad54898712e3f4228afcd05169cebb784 (diff) | |
src: Move POST_BOOTBLOCK_CAR to common postcodes and use it
This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific
postcodes into the common postcode list, and uses it for the
cache-as-RAM init as needed.
Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in
most of the others, the values were consolidated into 0x21. This will
change the value on some platforms.
Any conflicts should get sorted out later in the conversion process.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8527334e679a23006b77a5645f919aea76dd4926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/include/cpu/intel')
| -rw-r--r-- | src/include/cpu/intel/post_codes.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/include/cpu/intel/post_codes.h b/src/include/cpu/intel/post_codes.h index 3db0aeb939..6c1ca79f20 100644 --- a/src/include/cpu/intel/post_codes.h +++ b/src/include/cpu/intel/post_codes.h @@ -3,7 +3,6 @@ #ifndef CPU_INTEL_CAR_POST_CODES_H #define CPU_INTEL_CAR_POST_CODES_H -#define POST_BOOTBLOCK_CAR 0x20 #define POST_SOC_SET_DEF_MTRR_TYPE 0x21 #define POST_SOC_CLEAR_FIXED_MTRRS 0x22 // Intentional Duplicate #define POST_SOC_DETERMINE_CPU_ADDR_BITS 0x22 |