diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-02 08:44:47 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-05 01:38:15 +0000 |
| commit | 4e6b7907de07c9c7d4b01a6213a8e13e946398cb (patch) | |
| tree | d6cb8f208a588506710e36a38d141d9228af7483 /src/include/cpu/intel | |
| parent | 19c0ae540ea992b76eb65421381269def0a6328d (diff) | |
src: Fix MSR_PKG_CST_CONFIG_CONTROL register name
Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/include/cpu/intel')
| -rw-r--r-- | src/include/cpu/intel/speedstep.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 4b556b758b..5390781304 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -43,7 +43,7 @@ #define MSR_EBC_FREQUENCY_ID 0x2c #define MSR_FSB_FREQ 0xcd #define MSR_FSB_CLOCK_VCC 0xce -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_BASE_ADDR 0xe3 #define MSR_PMG_IO_CAPTURE_ADDR 0xe4 #define MSR_EXTENDED_CONFIG 0xee |