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| author | Gang Chen <gang.c.chen@intel.com> | 2024-07-11 06:51:43 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-09-13 11:09:50 +0000 |
| commit | 2f56049778bc98b0d215763c4f1d5d6bb6412e9f (patch) | |
| tree | 1001380b4198233a2bdfce7d8bbc6e5b328ca7a1 /src/include/cpu/intel/microcode.h | |
| parent | 95cf9c0052234cf19599c03ea214eff4a6ed3b65 (diff) | |
soc/intel/xeon_sp/gnr: Use default DCACHE_BSP_STACK_SIZE
For Xeon-SP, DCACHE_BSP_STACK_SIZE is by default 0x10000. For GNR,
this default size is enough. Use the default size so that more
CAR spaces could be saved for other purpose.
Change-Id: I68a79df150c4954ef8d703987d7c0bb446ba4cda
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84302
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/cpu/intel/microcode.h')
0 files changed, 0 insertions, 0 deletions