diff options
| author | Indrek Kruusa <indrek.kruusa@artecdesign.ee> | 2006-08-02 11:30:32 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2006-08-02 11:30:32 +0000 |
| commit | f4c0b596a21918b0d023a39096c99e3d44ef19be (patch) | |
| tree | c4f5b9e0ca92aa8ea39417baab3f6c907fb50256 /src/include/cpu/amd | |
| parent | 4278e99383c926e2056a92b4bebb885ee6fdbea6 (diff) | |
Geode LX: this patch adds configuration/status/self-test MSR definitions
for L2 cache and fixes wrong P2D defines.
This also patch adds L2 cache initialization for Geode LX CPU.
Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include/cpu/amd')
| -rw-r--r-- | src/include/cpu/amd/lxdef.h | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h index 6f04dd9364..9ee1627194 100644 --- a/src/include/cpu/amd/lxdef.h +++ b/src/include/cpu/amd/lxdef.h @@ -236,11 +236,17 @@ #define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8 #define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0 +/* ----- GX3 OK ---- */ + #define CPU_RCONF_BYPASS 0x180A #define CPU_RCONF_A0_BF 0x180B #define CPU_RCONF_C0_DF 0x180C #define CPU_RCONF_E0_FF 0x180D +/* ------------------------ */ + +/* ----- GX3 OK ---- */ + #define CPU_RCONF_SMM 0x180E #define RCONF_SMM_UPPER_SMMTOP_SHIFT 12 #define RCONF_SMM_UPPER_RCSMM_SHIFT 0 @@ -248,6 +254,9 @@ #define RCONF_SMM_LOWER_RCNORM_SHIFT 0 #define RCONF_SMM_LOWER_EN_SET (1<<8) +/* ------------------------ */ + + #define CPU_RCONF_DMM 0x180F #define RCONF_DMM_UPPER_DMMTOP_SHIFT 12 #define RCONF_DMM_UPPER_RCDMM_SHIFT 0 @@ -299,6 +308,15 @@ #define TSC_SUSP_SET (1<<5) #define SUSP_EN_SET (1<<12) +/* L2 cache*/ + +#define L2_CONFIG_MSR 0x1920 +#define L2_STATUS_MSR 0x1921 +#define L2_BIST_MSR 0x1926 + + + + /**/ /* VG GLIU0 port4*/ /**/ @@ -481,8 +499,8 @@ #define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM*/ #define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM*/ -#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC*/ -#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R*/ +#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2E) /* SCO should only be SC*/ // GX3 0x2D -> 0x2E +#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x2A) /* RO should only be R*/ // GX3 0x29 -> 0x2A #define MSR_GLIU1_SMM (MSR_GLIU1 + 0x23) /* BM*/ #define MSR_GLIU1_DMM (MSR_GLIU1 + 0x24) /* BM*/ #define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU*/ |