diff options
| author | Li-Ta Lo <ollie@lanl.gov> | 2006-03-20 21:18:53 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2006-03-20 21:18:53 +0000 |
| commit | af9484a2a8a88ad68c23a509b713646dda4c740b (patch) | |
| tree | 141e50584955815eef2b78e48563487c6f4e8bfe /src/include/cpu/amd | |
| parent | db44be9405ae4b62b525fb7dad80e20c499cc07b (diff) | |
resolve conflict
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include/cpu/amd')
| -rw-r--r-- | src/include/cpu/amd/gx2def.h | 41 |
1 files changed, 21 insertions, 20 deletions
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index b7ff4c0c87..36d59c30f9 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -7,7 +7,27 @@ #define GLCP_DELAY_CONTROLS 0x4c00000f #define GLCP_SYS_RSTPLL 0x4c000014 #define GLCP_DOTPLL 0x4c000015 -#define GLCP_CHIP_REVID 0x4c000017 +#define GLCP_CHIP_REVID 0x4c000017 + +/* GLCP_SYS_RSTPLL, Upper 32 bits */ +#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9 +#define GLCP_SYS_RSTPLL_VDIV_SHIFT 6 +#define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0 + +/* GLCP_SYS_RSTPLL, Lower 32 bits */ +#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26 +#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26) + +#define GLCP_SYS_RSTPLL_LOCKWAIT 24 +#define GLCP_SYS_RSTPLL_HOLDCOUNT 16 +#define GLCP_SYS_RSTPLL_BYPASS 15 +#define GLCP_SYS_RSTPLL_PD 14 +#define GLCP_SYS_RSTPLL_RESETPLL 13 +#define GLCP_SYS_RSTPLL_DDRMODE 10 +#define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9 +#define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8 +#define GLCP_SYS_RSTPLL_CHIP_RESET 0 + /* MSR routing as follows*/ /* MSB = 1 means not for CPU*/ /* next 3 bits 1st port*/ @@ -272,23 +292,4 @@ #define VG_GLD_MSR_CONFIG MSR_VG + 0x2001 #define VG_GLD_MSR_PM MSR_VG + 0x2004 - /* Upper 32 bits */ -#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9 -#define GLCP_SYS_RSTPLL_VDIV_SHIFT 6 -#define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0 - - /* Lower 32 bits */ -#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26 -#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26) - -#define GLCP_SYS_RSTPLL_LOCKWAIT 24 -#define GLCP_SYS_RSTPLL_HOLDCOUNT 16 -#define GLCP_SYS_RSTPLL_BYPASS 15 -#define GLCP_SYS_RSTPLL_PD 14 -#define GLCP_SYS_RSTPLL_RESETPLL 13 -#define GLCP_SYS_RSTPLL_DDRMODE 10 -#define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9 -#define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8 -#define GLCP_SYS_RSTPLL_CHIP_RESET 0 - #endif /* CPU_AMD_GX2DEF_H */ |