diff options
| author | Li-Ta Lo <ollie@lanl.gov> | 2006-03-13 21:58:43 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2006-03-13 21:58:43 +0000 |
| commit | 71eae20b305fc894f2d6e35bd5d58084153ea8b6 (patch) | |
| tree | 54096e3c09ca22adee49c18b095b23dad2a2dc50 /src/include/cpu/amd | |
| parent | ec9cdc980fe3f6c5037b76907550e1323958da75 (diff) | |
failed attempt to do early init for cs5535. Almost there but
still get garbage reading smbus.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include/cpu/amd')
| -rw-r--r-- | src/include/cpu/amd/gx2def.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index e69de29bb2..8f5a6d6dc9 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -0,0 +1,31 @@ +#ifndef CPU_AMD_GX2DEF_H +#define CPU_AMD_GX2DEF_H + +/* GeodeLink Control Processor Registers, GLIU1, Port 3 */ +#define GLCP_CLK_DIS_DELAY 0x4c000008 +#define GLCP_PMCLKDISABLE 0x4c000009 +#define GLCP_DELAY_CONTROLS 0x4c00000f +#define GLCP_SYS_RSTPLL 0x4c000014 +#define GLCP_DOTPLL 0x4c000015 + + + /* Upper 32 bits */ +#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9 +#define GLCP_SYS_RSTPLL_VDIV_SHIFT 6 +#define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0 + + /* Lower 32 bits */ +#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26 +#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26) + +#define GLCP_SYS_RSTPLL_LOCKWAIT 24 +#define GLCP_SYS_RSTPLL_HOLDCOUNT 16 +#define GLCP_SYS_RSTPLL_BYPASS 15 +#define GLCP_SYS_RSTPLL_PD 14 +#define GLCP_SYS_RSTPLL_RESETPLL 13 +#define GLCP_SYS_RSTPLL_DDRMODE 10 +#define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9 +#define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8 +#define GLCP_SYS_RSTPLL_CHIP_RESET 0 + +#endif /* CPU_AMD_GX2DEF_H */ |