Applying YhLu's patch from issue 37.

a. apic id liftting to way that kernel like and let bsp
   to stay with 0
b. hw memhole: solve if hole_startk == some node
   basek
                 
This, together with the previous one will break most of 
the tree, but Yinghai Lu is really good
at fixing things, so...

   


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 99 insertions, 0 deletions

diff --git a/src/include/cpu/amd/model_fxx_msr.h b/src/include/cpu/amd/model_fxx_msr.h
new file mode 100644
index 0000000000..b4795cbbb2
--- /dev/null
+++ b/src/include/cpu/amd/model_fxx_msr.h
@@ -0,0 +1,21 @@
+#ifndef CPU_AMD_MODEL_FXX_MSR_H
+#define CPU_AMD_MODEL_FXX_MSR_H
+
+#define HWCR_MSR			0xC0010015
+#define NB_CFG_MSR			0xC001001f
+#define LS_CFG_MSR                      0xC0011020
+#define IC_CFG_MSR			0xC0011021
+#define DC_CFG_MSR			0xC0011022
+#define BU_CFG_MSR			0xC0011023
+
+
+#define CPU_ID_FEATURES_MSR		0xc0011004
+
+/* D0 only */
+#define CPU_ID_HYPER_EXT_FEATURES	0xc001100d
+/* E0 only */
+#define LOGICAL_CPUS_NUM_MSR		0xc001100d
+
+#define CPU_ID_EXT_FEATURES_MSR		0xc0011005
+
+#endif /* CPU_AMD_MODEL_FXX_MSR_H */
diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h
new file mode 100644
index 0000000000..4c2a7ce940
--- /dev/null
+++ b/src/include/cpu/amd/model_fxx_rev.h
@@ -0,0 +1,78 @@
+#include <arch/cpu.h>
+
+static inline int is_cpu_rev_a0(void)
+{
+	return (cpuid_eax(1) & 0xfffef) == 0x0f00;
+}
+static inline int is_cpu_pre_c0(void)
+{
+        return (cpuid_eax(1) & 0xfffef) < 0x0f48;
+}
+
+static inline int is_cpu_c0(void)
+{
+        return (cpuid_eax(1) & 0xfffef) == 0x0f48;
+}
+
+static inline int is_cpu_pre_b3(void)
+{
+        return (cpuid_eax(1) & 0xfffef) < 0x0f41;
+}
+
+static inline int is_cpu_b3(void)
+{
+        return (cpuid_eax(1) & 0xfffef) == 0x0f41;
+}
+//AMD_D0_SUPPORT
+static inline int is_cpu_pre_d0(void)
+{
+        return (cpuid_eax(1) & 0xfff0f) < 0x10f00;
+}
+
+static inline int is_cpu_d0(void)
+{
+        return (cpuid_eax(1) & 0xfff0f) == 0x10f00;
+}
+
+//AMD_E0_SUPPORT
+static inline int is_cpu_pre_e0(void)
+{
+        return (cpuid_eax(1) & 0xfff0f) < 0x20f00;
+}
+
+static inline int is_cpu_e0(void)
+{
+        return (cpuid_eax(1) & 0xfff00) == 0x20f00;
+}
+
+
+#ifdef __ROMCC__
+static int is_e0_later_in_bsp(int nodeid)
+{
+        uint32_t val;
+        uint32_t val_old;
+        int e0_later;
+        if(nodeid==0) { // we don't need to do that for node 0 in core0/node0
+                return !is_cpu_pre_e0();
+        }
+        // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
+        device_t dev;
+        dev = PCI_DEV(0, 0x18+nodeid,2);
+        val_old = pci_read_config32(dev, 0x80);
+        val = val_old;
+        val |= (1<<3);
+        pci_write_config32(dev, 0x80, val);
+        val = pci_read_config32(dev, 0x80);
+        e0_later = !!(val & (1<<3));
+        if(e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
+                pci_write_config32(dev, 0x80, val_old); // restore it
+        }
+
+        return e0_later;
+}
+#else
+int is_e0_later_in_bsp(int nodeid); //defined model_fxx_init.c
+#endif
+
+
+