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| author | Scott Duplichan <scott@notabs.org> | 2010-11-13 19:07:59 +0000 |
|---|---|---|
| committer | Scott Duplichan <scott@notabs.org> | 2010-11-13 19:07:59 +0000 |
| commit | f3cce2f3c4ff4af4a386bddd49c92a55ad9cefa2 (patch) | |
| tree | 2961bfdba8f650fca44d04fe1232c76c71adda05 /src/include/cpu/amd/mtrr.h | |
| parent | 5960fb3dbd5c942d3c11f06dcd0c55f940444260 (diff) | |
MTRR related improvements for AMD family 10h and family 0Fh systems
-- When building for UMA, reduce the limit for DRAM below 4GB
from E0000000 to C0000000. This is needed to accomodate the
UMA frame buffer.
-- Correct problem where msr C0010010 bits 21 and 22 (MtrrTom2En
and Tom2ForceMemTypeWB) are not set consistently across cores.
-- Enable TOM2 only if DRAM is present above 4GB.
-- Use AMD Tom2ForceMemTypeWB feature to avoid the need for
variable MTRR ranges above 4GB.
-- Add above4gb flag argument to function x86_setup_var_mtrrs. Clearing
this flag causes x86_setup_var_mtrrs() to omit MTRR ranges for
DRAM above 4GB. AMD systems use this option to conserve MTRRs.
-- Northbridge.c change to deduct UMA memory from DRAM size reported
by ram_resource. This corrects a problem where mtrr.c generates an
unexpected variable MTRR range.
-- Correct problem causing build failure when CONFIG_GFXUMA=1 and
CONFIG_VAR_MTRR_HOLE=0.
-- Reserve the UMA DRAM range for AMD K8 as is already done for AMD
family 10h.
Tested with mahogany on ECS A780G-GM with 2GB and 4GB.
Tested with mahogany_fam10 on ECS A780G-GM with 2GB and 4GB.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include/cpu/amd/mtrr.h')
| -rw-r--r-- | src/include/cpu/amd/mtrr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index e866fb9511..6e25aa3e5e 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -8,6 +8,7 @@ #define MTRR_WRITE_MEM (1 << 3) #define SYSCFG_MSR 0xC0010010 +#define SYSCFG_MSR_TOM2WB (1 << 22) #define SYSCFG_MSR_TOM2En (1 << 21) #define SYSCFG_MSR_MtrrVarDramEn (1 << 20) #define SYSCFG_MSR_MtrrFixDramModEn (1 << 19) |