diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-24 00:34:15 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-31 03:42:11 +0000 |
commit | d840eb5719e51e1946ab322c0eb94defc72dde1d (patch) | |
tree | d74fa8bb59692dbb92fed137363d61f427dda2d0 /src/include/cpu/amd/model_fxx_rev.h | |
parent | 4979ffc5cb267c7b0a5ad84c8bb9729e6b5613b1 (diff) |
Remove AMD K8 cpu and northbridge support
Change-Id: I9c53dfa93bf906334f5c80e4525a1c27153656a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/include/cpu/amd/model_fxx_rev.h')
-rw-r--r-- | src/include/cpu/amd/model_fxx_rev.h | 131 |
1 files changed, 0 insertions, 131 deletions
diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h deleted file mode 100644 index 6fb6194137..0000000000 --- a/src/include/cpu/amd/model_fxx_rev.h +++ /dev/null @@ -1,131 +0,0 @@ -#ifndef __CPU_AMD_MODEL_FXX_REV_H__ -#define __CPU_AMD_MODEL_FXX_REV_H__ - -#include <arch/cpu.h> -#include <arch/io.h> - -int init_processor_name(void); - -static inline int is_cpu_rev_a0(void) -{ - return (cpuid_eax(1) & 0xfffef) == 0x0f00; -} -static inline int is_cpu_pre_c0(void) -{ - return (cpuid_eax(1) & 0xfffef) < 0x0f48; -} - -static inline int is_cpu_c0(void) -{ - return (cpuid_eax(1) & 0xfffef) == 0x0f48; -} - -static inline int is_cpu_pre_b3(void) -{ - return (cpuid_eax(1) & 0xfffef) < 0x0f41; -} - -static inline int is_cpu_b3(void) -{ - return (cpuid_eax(1) & 0xfffef) == 0x0f41; -} -//AMD_D0_SUPPORT -static inline int is_cpu_pre_d0(void) -{ - return (cpuid_eax(1) & 0xfff0f) < 0x10f00; -} - -static inline int is_cpu_d0(void) -{ - return (cpuid_eax(1) & 0xfff0f) == 0x10f00; -} - -//AMD_E0_SUPPORT -static inline int is_cpu_pre_e0(void) -{ - return (cpuid_eax(1) & 0xfff0f) < 0x20f00; -} - -static inline int is_cpu_e0(void) -{ - return (cpuid_eax(1) & 0xfff00) == 0x20f00; -} - -//AMD_F0_SUPPORT -static inline int is_cpu_pre_f0(void) -{ - return (cpuid_eax(1) & 0xfff0f) < 0x40f00; -} - -static inline int is_cpu_f0(void) -{ - return (cpuid_eax(1) & 0xfff00) == 0x40f00; -} - -static inline int is_cpu_pre_f2(void) -{ - return (cpuid_eax(1) & 0xfff0f) < 0x40f02; -} - -#ifdef __PRE_RAM__ -static inline int is_e0_later_in_bsp(int nodeid) -{ - uint32_t val; - uint32_t val_old; - int e0_later; - - if (IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)) - return 1; - - // we don't need to do that for node 0 in core0/node0 - if (nodeid == 0) - return !is_cpu_pre_e0(); - - // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 - // always 0 - pci_devfn_t dev; - dev = PCI_DEV(0, 0x18+nodeid, 2); - val_old = pci_read_config32(dev, 0x80); - val = val_old; - val |= (1<<3); - pci_write_config32(dev, 0x80, val); - val = pci_read_config32(dev, 0x80); - e0_later = !!(val & (1<<3)); - - // pre_e0 bit 3 always be 0 and can not be changed - if (e0_later) - pci_write_config32(dev, 0x80, val_old); // restore it - - return e0_later; -} - -static inline int is_cpu_f0_in_bsp(int nodeid) -{ - uint32_t dword; - pci_devfn_t dev; - if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)) - return 0; - dev = PCI_DEV(0, 0x18+nodeid, 3); - dword = pci_read_config32(dev, 0xfc); - return (dword & 0xfff00) == 0x40f00; -} - -static inline int is_cpu_pre_f2_in_bsp(int nodeid) -{ - uint32_t dword; - pci_devfn_t dev; - - if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)) - return 1; - dev = PCI_DEV(0, 0x18+nodeid, 3); - dword = pci_read_config32(dev, 0xfc); - return (dword & 0xfff0f) < 0x40f02; -} - -#else - -int is_e0_later_in_bsp(int nodeid); -int is_cpu_f0_in_bsp(int nodeid); - -#endif -#endif /* __CPU_AMD_MODEL_FXX_REV_H__ */ |