diff options
| author | Richard Smith <smithbone@gmail.com> | 2006-08-25 05:01:30 +0000 |
|---|---|---|
| committer | Richard Smith <smithbone@gmail.com> | 2006-08-25 05:01:30 +0000 |
| commit | 59ba228f921169bb12347932237c7500ccd58b41 (patch) | |
| tree | 3f044b86c34ff6fd843dcebe5e62b29afdfab0d4 /src/include/cpu/amd/gx2def.h | |
| parent | 689c1448392ed93dfafc51a2dba39ba37631ce29 (diff) | |
- Added suport for enabling USB P4 on the olpc
USB P4 is disabled by default and we need to setup the mux bits proper
to make it work. This is the frame work for that. All thats needed
is the right address values
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include/cpu/amd/gx2def.h')
| -rw-r--r-- | src/include/cpu/amd/gx2def.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index 8e64659120..06f9a6372b 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -731,10 +731,14 @@ /* */ /* USB2*/ /* */ -#define USB2_SB_GLD_MSR_CAP ( MSR_SB_USB2 + 0x00) -#define USB2_SB_GLD_MSR_CONF ( MSR_SB_USB2 + 0x01) -#define USB2_SB_GLD_MSR_PM ( MSR_SB_USB2 + 0x04) +#define USB2_SB_GLD_MSR_CAP ( MSR_SB_USB2 + 0x00) +#define USB2_SB_GLD_MSR_CONF ( MSR_SB_USB2 + 0x01) +#define USB2_SB_GLD_MSR_PM ( MSR_SB_USB2 + 0x04) +#define USB2_SB_GLD_MSR_OHCI_BASE ( MSR_SB_USB2 + 0x08) +#define USB2_SB_GLD_MSR_EHCI_BASE ( MSR_SB_USB2 + 0x09) +#define USB2_SB_GLD_MSR_DEVCTL_BASE ( MSR_SB_USB2 + 0x0A) +#define USB2_SB_GLD_MSR_UOC_BASE ( MSR_SB_USB2 + 0x0B) /* Option controller base */ /* */ /* ATA*/ |