diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-05-05 19:46:09 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-05-12 06:16:05 +0000 |
| commit | 8d2b0dcc4447e5189bf993f9b4854dfbd08fb55c (patch) | |
| tree | a7547d6599506e43e52621b880e3e5cc6096d537 /src/include/console | |
| parent | 38e4a2d4cf3398d56640b03371ff1bd08b30aff5 (diff) | |
include/console: Rename and update POST_ENTRY_RAMSTAGE postcode
Rename and update POST_ENTRY_RAMSTAGE postcode value from 0x80 to 0x6f
to make the ramstage postcodes appear in an incremental order.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/include/console')
| -rw-r--r-- | src/include/console/post_codes.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 9682e4db6c..9b2398c6fa 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -112,6 +112,14 @@ #define POST_PRE_HARDWAREMAIN 0x6e /** + * \brief Entry into coreboot in RAM stage main() + * + * This is the first call in hardwaremain.c. If this code is POSTed, then + * ramstage has successfully loaded and started executing. + */ +#define POST_ENTRY_HARDWAREMAIN 0x6f + +/** * \brief Before Device Probe * * Boot State Machine: bs_pre_device() @@ -196,14 +204,6 @@ #define POST_BS_PAYLOAD_BOOT 0x7b /** - * \brief Entry into coreboot in RAM stage main() - * - * This is the first call in hardwaremain.c. If this code is POSTed, then - * ramstage has successfully loaded and started executing. - */ -#define POST_ENTRY_RAMSTAGE 0x80 - -/** * \brief Before calling FSP Notify before End of Firmware * * Going to call into FSP binary for Notify phase |