diff options
author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-07 17:45:12 -0800 |
---|---|---|
committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-13 17:23:37 +0100 |
commit | 6a566d7fbee8e81fa22916a29339e5991872edfb (patch) | |
tree | 21840b8f2965439422e809ab56f9ef19cdccf4bd /src/include/console | |
parent | d0f26fcea2fdab02d9b9fc1fceb9e782694a55bc (diff) |
src/include: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
Changed a few comments to reduce line length. File
src/include/cpu/amd/vr.h was skipped.
TEST=Build and run on Galileo Gen2
Change-Id: Ie3c07111acc1f89923fb31135684a6d28a505b61
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18687
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/include/console')
-rw-r--r-- | src/include/console/console.h | 3 | ||||
-rw-r--r-- | src/include/console/early_print.h | 18 | ||||
-rw-r--r-- | src/include/console/ne2k.h | 15 | ||||
-rw-r--r-- | src/include/console/post_codes.h | 7 | ||||
-rw-r--r-- | src/include/console/qemu_debugcon.h | 5 | ||||
-rw-r--r-- | src/include/console/spi.h | 5 | ||||
-rw-r--r-- | src/include/console/uart.h | 25 | ||||
-rw-r--r-- | src/include/console/usb.h | 15 |
8 files changed, 70 insertions, 23 deletions
diff --git a/src/include/console/console.h b/src/include/console/console.h index 7edce52ff8..3100ae2d55 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -48,7 +48,8 @@ void __attribute__ ((noreturn)) die(const char *msg); #if __CONSOLE_ENABLE__ asmlinkage void console_init(void); int console_log_level(int msg_level); -int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +int do_printk(int msg_level, const char *fmt, ...) + __attribute__((format(printf, 2, 3))); void do_putchar(unsigned char byte); #define printk(LEVEL, fmt, args...) \ diff --git a/src/include/console/early_print.h b/src/include/console/early_print.h index cde501a4ec..2e6a2461b7 100644 --- a/src/include/console/early_print.h +++ b/src/include/console/early_print.h @@ -25,7 +25,8 @@ /* While in romstage, console loglevel is built-time constant. * With ROMCC we inline this test with help from preprocessor. */ -#define console_log_level(msg_level) (msg_level <= CONFIG_DEFAULT_CONSOLE_LOGLEVEL) +#define console_log_level(msg_level) \ + (msg_level <= CONFIG_DEFAULT_CONSOLE_LOGLEVEL) #define CALL_CONSOLE_TX(loglevel, tx_func, x) \ do { \ @@ -35,11 +36,16 @@ } \ } while (0) -#define __console_tx_char(level, x) CALL_CONSOLE_TX(level, console_tx_byte, x) -#define __console_tx_hex8(level, x) CALL_CONSOLE_TX(level, console_tx_hex8, x) -#define __console_tx_hex16(level, x) CALL_CONSOLE_TX(level, console_tx_hex16, x) -#define __console_tx_hex32(level, x) CALL_CONSOLE_TX(level, console_tx_hex32, x) -#define __console_tx_string(level, x) CALL_CONSOLE_TX(level, console_tx_string, x) +#define __console_tx_char(level, x) \ + CALL_CONSOLE_TX(level, console_tx_byte, x) +#define __console_tx_hex8(level, x) \ + CALL_CONSOLE_TX(level, console_tx_hex8, x) +#define __console_tx_hex16(level, x) \ + CALL_CONSOLE_TX(level, console_tx_hex16, x) +#define __console_tx_hex32(level, x) \ + CALL_CONSOLE_TX(level, console_tx_hex32, x) +#define __console_tx_string(level, x) \ + CALL_CONSOLE_TX(level, console_tx_string, x) #define print_emerg(STR) __console_tx_string(BIOS_EMERG, STR) #define print_alert(STR) __console_tx_string(BIOS_ALERT, STR) diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index d7974b5a33..ea2a139ad2 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -28,9 +28,18 @@ void ne2k_transmit(unsigned int eth_nic_base); #endif #if CONFIG_CONSOLE_NE2K && (ENV_ROMSTAGE || ENV_RAMSTAGE) -static inline void __ne2k_init(void) { ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); } -static inline void __ne2k_tx_byte(u8 data) { ne2k_append_data_byte(data, CONFIG_CONSOLE_NE2K_IO_PORT); } -static inline void __ne2k_tx_flush(void) { ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); } +static inline void __ne2k_init(void) +{ + ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); +} +static inline void __ne2k_tx_byte(u8 data) +{ + ne2k_append_data_byte(data, CONFIG_CONSOLE_NE2K_IO_PORT); +} +static inline void __ne2k_tx_flush(void) +{ + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +} #else static inline void __ne2k_init(void) {} static inline void __ne2k_tx_byte(u8 data) {} diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index e1a640cab7..f08796cf72 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -347,12 +347,13 @@ /* * The following POST codes are taken from src/include/cpu/amd/geode_post_code.h * They overlap with previous codes, and most are not even used - * Some mainboards still require them, but they are deprecated. We want to consolidate - * our own POST code structure with the codes above. + * Some mainboards still require them, but they are deprecated. We want to + * consolidate our own POST code structure with the codes above. * * standard AMD post definitions for the AMD Geode */ -#define POST_Output_Port (0x080) /* port to write post codes to*/ +/* port to write post codes to */ +#define POST_Output_Port (0x080) #define POST_preSioInit (0x000) #define POST_clockInit (0x001) diff --git a/src/include/console/qemu_debugcon.h b/src/include/console/qemu_debugcon.h index 257ae581e5..544442a662 100644 --- a/src/include/console/qemu_debugcon.h +++ b/src/include/console/qemu_debugcon.h @@ -9,7 +9,10 @@ void qemu_debugcon_tx_byte(unsigned char data); #if CONFIG_CONSOLE_QEMU_DEBUGCON && (ENV_ROMSTAGE || ENV_RAMSTAGE) static inline void __qemu_debugcon_init(void) { qemu_debugcon_init(); } -static inline void __qemu_debugcon_tx_byte(u8 data) { qemu_debugcon_tx_byte(data); } +static inline void __qemu_debugcon_tx_byte(u8 data) +{ + qemu_debugcon_tx_byte(data); +} #else static inline void __qemu_debugcon_init(void) {} static inline void __qemu_debugcon_tx_byte(u8 data) {} diff --git a/src/include/console/spi.h b/src/include/console/spi.h index 32741fbdd8..4d281acd77 100644 --- a/src/include/console/spi.h +++ b/src/include/console/spi.h @@ -27,7 +27,10 @@ void spiconsole_tx_byte(unsigned char c); #if __CONSOLE_SPI_ENABLE__ static inline void __spiconsole_init(void) { spiconsole_init(); } -static inline void __spiconsole_tx_byte(u8 data) { spiconsole_tx_byte(data); } +static inline void __spiconsole_tx_byte(u8 data) +{ + spiconsole_tx_byte(data); +} #else static inline void __spiconsole_init(void) {} static inline void __spiconsole_tx_byte(u8 data) {} diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 45faf0ad6f..07ac763932 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -60,9 +60,18 @@ void oxford_remap(unsigned int new_base); ENV_POSTCAR || (ENV_SMM && CONFIG_DEBUG_SMI))) #if __CONSOLE_SERIAL_ENABLE__ -static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); } -static inline void __uart_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); } -static inline void __uart_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_CONSOLE); } +static inline void __uart_init(void) +{ + uart_init(CONFIG_UART_FOR_CONSOLE); +} +static inline void __uart_tx_byte(u8 data) +{ + uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); +} +static inline void __uart_tx_flush(void) +{ + uart_tx_flush(CONFIG_UART_FOR_CONSOLE); +} #else static inline void __uart_init(void) {} static inline void __uart_tx_byte(u8 data) {} @@ -72,9 +81,15 @@ static inline void __uart_tx_flush(void) {} #if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) #define CONFIG_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE static inline void __gdb_hw_init(void) { uart_init(CONFIG_UART_FOR_GDB); } -static inline void __gdb_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_GDB, data); } +static inline void __gdb_tx_byte(u8 data) +{ + uart_tx_byte(CONFIG_UART_FOR_GDB, data); +} static inline void __gdb_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_GDB); } -static inline u8 __gdb_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_GDB); } +static inline u8 __gdb_rx_byte(void) +{ + return uart_rx_byte(CONFIG_UART_FOR_GDB); +} #endif #endif /* __ROMCC__ */ diff --git a/src/include/console/usb.h b/src/include/console/usb.h index d52ea87536..1b153ef8e6 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -35,7 +35,10 @@ int usb_can_rx_byte(int idx); #if __CONSOLE_USB_ENABLE__ static inline void __usbdebug_init(void) { usbdebug_init(); } -static inline void __usb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); } +static inline void __usb_tx_byte(u8 data) +{ + usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); +} static inline void __usb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_CONSOLE); } #else static inline void __usbdebug_init(void) {} @@ -47,9 +50,15 @@ static inline void __usb_tx_flush(void) {} #if 0 && CONFIG_GDB_STUB && \ ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) static inline void __gdb_hw_init(void) { usbdebug_init(); } -static inline void __gdb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_GDB, data); } +static inline void __gdb_tx_byte(u8 data) +{ + usb_tx_byte(USB_PIPE_FOR_GDB, data); +} static inline void __gdb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_GDB); } -static inline u8 __gdb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_GDB); } +static inline u8 __gdb_rx_byte(void) +{ + return usb_rx_byte(USB_PIPE_FOR_GDB); +} #endif #endif /* _CONSOLE_USB_H_ */ |