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author | Jamie Ryu <jamie.m.ryu@intel.com> | 2020-10-14 14:21:37 -0700 |
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committer | Furquan Shaikh <furquan@google.com> | 2020-11-18 01:26:52 +0000 |
commit | 6ecd4c65e7d64ad6ed6d4f680b22d12413ea01ae (patch) | |
tree | 128902294dd86bc5347337353b14c2581f5b0a9c /src/include/bootblock_common.h | |
parent | 361e3646357504ef8843e3f85b35a1a966b88fe1 (diff) |
mb/google/volteer: Update flashmap descriptor to add ME_RW_A/B region
The current CSE firmware update implementation adds CSE RW binary to
FW_MAIN_A/B and this increases the boot time due to the size increase
of these regions leading to higher loading and hashing time.
To mitigate this issue, CSE RW binary is moved from FW_MAIN_A/B to new
region, ME_RW_A/B under RW_SECTON_A/B, and this updates the flashmap to
add ME_RW_A/B region for CSE RW binary.
BUG=b:169077783
TEST=build with cse rw binary, flash and verify volteer2 boots to OS.
Verify me_rw binary is added to ME_RW_A/B region.
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I87da3824933ed2dd8e8ed0fed8686d2a3527faea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46431
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/bootblock_common.h')
0 files changed, 0 insertions, 0 deletions