diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-03-26 13:09:39 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-29 20:09:36 +0100 |
| commit | bc07f5d93552640793254ce003937ec646120a21 (patch) | |
| tree | 091f2189c38629d64579c5864220f8b2f2039db0 /src/include/boot | |
| parent | f567f16af4c3cbfcadc3bc5c44b569a592829262 (diff) | |
x86: add rom cache variable MTRR index to tables
Downstream payloads may need to take advantage of caching the
ROM for performance reasons. Add the ability to communicate the
variable range MTRR index to use to perform the caching enablement.
An example usage implementation would be to obtain the variable MTRR
index that covers the ROM from the coreboot tables. Then one would
disable caching and change the MTRR type from uncacheable to
write-protect and enable caching. The opposite sequence is required
to tearn down the caching.
Change-Id: I4d486cfb986629247ab2da7818486973c6720ef5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2919
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/include/boot')
| -rw-r--r-- | src/include/boot/coreboot_tables.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index f624ac1e1a..a7e4ab0500 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -250,6 +250,14 @@ struct lb_vboot_handoff { uint32_t vboot_handoff_size; }; +#define LB_TAG_X86_ROM_MTRR 0x0021 +struct lb_x86_rom_mtrr { + uint32_t tag; + uint32_t size; + /* The variable range MTRR index covering the ROM. */ + uint32_t index; +}; + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ |