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| author | Aamir Bohra <aamir.bohra@intel.com> | 2017-05-11 20:31:06 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-05-22 18:12:05 +0200 |
| commit | 5196642870df642102699613642d412561f6609d (patch) | |
| tree | 912f418f59c98c344205dda6716ebd6787f8f732 /src/include/base3.h | |
| parent | 2d689f9e0d281b7ebe99340731511b51d9af21cc (diff) | |
soc/intel/skylake: Use Intel PCIe common code
Change-Id: Ia9fa22c30fffb1907320667ac37f55db9f3cb7b3
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Diffstat (limited to 'src/include/base3.h')
0 files changed, 0 insertions, 0 deletions