soc/amd/genoa/devicetree: fix MMIO base addresses

The base addresses of I2C 5 and I3C 3 were wrong and all I3C controllers
should use the base address of the 4kiB block where all registers of
that I3C controller are located in. PPR #55901 Rev 0.26 was used as a
reference.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1c983d4a709000ef7963b96228322603b98728aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

0 files changed, 0 insertions, 0 deletions