soc/amd/acpi: Move ACPI IVRS generation to coreboot

Add code for IVRS generation to coreboot. Publish coreboot generated
structure rather than IVRS generated by FSP binary.

Reference Doc: 48882_IOMMU_3.05_PUB.pdf

BUG=b:155307433
TEST=Boot trembyle to shell and extract and compare IVRS tables and make
sure they cover the same devices.

Change-Id: I693f4399766c71c3ad53539634c65ba59afd0fe1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

1 files changed, 91 insertions, 2 deletions

diff --git a/src/include/acpi/acpi_ivrs.h b/src/include/acpi/acpi_ivrs.h
index de3bdeab4d..fe0aa408fd 100644
--- a/src/include/acpi/acpi_ivrs.h
+++ b/src/include/acpi/acpi_ivrs.h
@@ -42,6 +42,7 @@
 
 /* Extended Feature Support */
 #define IVINFO_EFR_SUPPORTED			0x01
+#define EFR_FEATURE_SUP				(1 << 27)
 
 /* IVHD Flags Field */
 #define IVHD_FLAG_PPE_SUP			(1 << 7) /* Type 10h only */
@@ -63,6 +64,7 @@
 #define IOMMU_FEATURE_PN_BANKS_SHIFT		17
 #define IOMMU_FEATURE_PN_COUNTERS_SHIFT		13
 #define IOMMU_FEATURE_PA_SMAX_SHIFT		8	 /* Type 10h only */
+#define IOMMU_FEATURE_GLX_SHIFT			3
 
 #define IOMMU_FEATURE_HE_SUP			(1 << 7) /* Type 10h only */
 #define IOMMU_FEATURE_GA_SUP			(1 << 6) /* Type 10h only */
@@ -70,8 +72,9 @@
 #define IOMMU_FEATURE_GLX_SINGLE_LEVEL		(0 << 3) /* Type 10h only */
 #define IOMMU_FEATURE_GLX_TWO_LEVEL		(1 << 3) /* Type 10h only */
 #define IOMMU_FEATURE_GLX_THREE_LEVEL		(2 << 3) /* Type 10h only */
-#define IOMMU_FEATURE_GT_SUP			(1 << 1) /* Type 10h only */
-#define IOMMU_FEATURE_NX_SUP			(1 << 0) /* Type 10h only */
+#define IOMMU_FEATURE_GT_SUP			(1 << 2) /* Type 10h only */
+#define IOMMU_FEATURE_NX_SUP			(1 << 1) /* Type 10h only */
+#define IOMMU_FEATURE_XT_SUP			(1 << 0)
 
 /* IVHD Device Entry Type Codes */
 #define IVHD_DEV_4_BYTE_ALL			0x01
@@ -108,6 +111,64 @@
 #define IVHD_UID_INT				0x01
 #define IVHD_UID_STRING				0x02
 
+#define IOMMU_CAP_ID				0x0f
+
+/* MMIO Offset 0x30: IOMMU Extended Feature Register */
+#define MMIO_EXT_FEATURE_PRE_F_SUP_SHIFT	0
+#define MMIO_EXT_FEATURE_PRE_F_SUP		(0x1 << MMIO_EXT_FEATURE_PRE_F_SUP_SHIFT)
+#define MMIO_EXT_FEATURE_PPR_SUP_SHIFT		1
+#define MMIO_EXT_FEATURE_PPR_SUP		(0x1 << MMIO_EXT_FEATURE_PPR_SUP_SHIFT)
+#define MMIO_EXT_FEATURE_XT_SUP_SHIFT		2
+#define MMIO_EXT_FEATURE_XT_SUP			(0x1 << MMIO_EXT_FEATURE_XT_SUP_SHIFT)
+#define MMIO_EXT_FEATURE_NX_SUP_SHIFT		3
+#define MMIO_EXT_FEATURE_NX_SUP			(0x1 << MMIO_EXT_FEATURE_NX_SUP_SHIFT)
+#define MMIO_EXT_FEATURE_GT_SUP_SHIFT		4
+#define MMIO_EXT_FEATURE_GT_SUP			(0x1 << MMIO_EXT_FEATURE_GT_SUP_SHIFT)
+#define MMIO_EXT_FEATURE_IA_SUP_SHIFT		6
+#define MMIO_EXT_FEATURE_IA_SUP			(0x1 << MMIO_EXT_FEATURE_IA_SUP_SHIFT)
+#define MMIO_EXT_FEATURE_GA_SUP_SHIFT		7
+#define MMIO_EXT_FEATURE_GA_SUP			(0x1 << MMIO_EXT_FEATURE_GA_SUP_SHIFT)
+#define MMIO_EXT_FEATURE_HE_SUP_SHIFT		8
+#define MMIO_EXT_FEATURE_HE_SUP			(0x1 << MMIO_EXT_FEATURE_HE_SUP_SHIFT)
+#define MMIO_EXT_FEATURE_PC_SUP_SHIFT		9
+#define MMIO_EXT_FEATURE_PC_SUP			(0x1 << MMIO_EXT_FEATURE_PC_SUP_SHIFT)
+#define MMIO_EXT_FEATURE_HATS_SHIFT		10
+#define MMIO_EXT_FEATURE_HATS_MASK		(0x3 << MMIO_EXT_FEATURE_HATS_SHIFT)
+#define MMIO_EXT_FEATURE_GATS_SHIFT		12
+#define MMIO_EXT_FEATURE_GATS_MASK		(0x3 << MMIO_EXT_FEATURE_GATS_SHIFT)
+#define MMIO_EXT_FEATURE_GLX_SHIFT		14
+#define MMIO_EXT_FEATURE_GLX_SUP_MASK		(0x3 << MMIO_EXT_FEATURE_GLX_SHIFT)
+#define MMIO_EXT_FEATURE_SMI_F_SUP_SHIFT	16
+#define MMIO_EXT_FEATURE_SMI_F_SUP_MASK		(0x3 << MMIO_EXT_FEATURE_SMI_F_SUP_SHIFT)
+#define MMIO_EXT_FEATURE_SMI_FRC_SHIFT		18
+#define MMIO_EXT_FEATURE_SMI_FRC_MASK		(0x7 << MMIO_EXT_FEATURE_SMI_FRC_SHIFT)
+#define MMIO_EXT_FEATURE_GAM_SUP_SHIFT		21
+#define MMIO_EXT_FEATURE_GAM_SUP_MASK		(0x7 << MMIO_EXT_FEATURE_GAM_SUP_SHIFT)
+#define MMIO_EXT_FEATURE_PAS_MAX_SHIFT		32
+#define MMIO_EXT_FEATURE_PAS_MAX_MASK		(0x1fULL << MMIO_EXT_FEATURE_PAS_MAX_SHIFT)
+
+/* MMIO Offset 0x18: IOMMU Control Register */
+#define MMIO_CTRL_IOMMU_EN			(1 << 0)
+#define MMIO_CTRL_HT_TUN_EN			(1 << 1)
+#define MMIO_CTRL_PASS_PW			(1 << 8)
+#define MMIO_CTRL_RES_PASS_PW			(1 << 9)
+#define MMIO_CTRL_COHERENT			(1 << 10)
+#define MMIO_CTRL_ISOC				(1 << 11)
+
+/* MMIO Offset 0x4000: Counter Configuration Register */
+#define MMIO_CNT_CFG_N_CNT_BANKS_SHIFT		12
+#define MMIO_CNT_CFG_N_COUNTER_BANKS		(0x3f << MMIO_CNT_CFG_N_CNT_BANKS_SHIFT)
+#define MMIO_CNT_CFG_N_COUNTER_SHIFT		7
+#define MMIO_CNT_CFG_N_COUNTER			(0xf << MMIO_CNT_CFG_N_COUNTER_SHIFT)
+
+/* Capability offset 0 */
+#define CAP_OFFSET_0_IOTLB_SP_SHIFT		24
+#define CAP_OFFSET_0_IOTLB_SP			(1 << CAP_OFFSET_0_IOTLB_SP_SHIFT)
+
+/// Capability offset 10h
+#define CAP_OFFSET_10_MSI_NUM_PPR_SHIFT		27
+#define CAP_OFFSET_10_MSI_NUM_PPR		(0x1f << CAP_OFFSET_10_MSI_NUM_PPR_SHIFT)
+
 /* IVHD (I/O Virtualization Hardware Definition Block) 4-byte entry */
 typedef struct ivrs_ivhd_generic {
 	uint8_t type;
@@ -125,6 +186,24 @@ typedef struct ivrs_ivhd_alias {
 	uint8_t reserved2;
 } __packed ivrs_ivhd_alias_t;
 
+/* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 40h */
+typedef struct acpi_ivrs_ivhd_40 {
+	uint8_t type;
+	uint8_t flags;
+	uint16_t length;
+	uint16_t device_id;
+	uint16_t capability_offset;
+	uint32_t iommu_base_low;
+	uint32_t iommu_base_high;
+	uint16_t pci_segment_group;
+	uint16_t iommu_info;
+	uint32_t iommu_attributes;
+	uint32_t efr_reg_image_low;
+	uint32_t efr_reg_image_high;
+	uint32_t reserved[2];
+	uint8_t entry[0];
+} __packed acpi_ivrs_ivhd40_t;
+
 typedef struct ivrs_ivhd_extended {
 	uint8_t type;
 	uint16_t dev_id;
@@ -141,4 +220,14 @@ typedef struct ivrs_ivhd_special {
 	uint8_t variety;
 } __packed ivrs_ivhd_special_t;
 
+typedef struct ivrs_ivhd_f0_entry {
+	uint8_t type;
+	uint16_t dev_id;
+	uint8_t dte_setting;
+	uint8_t hardware_id[8];
+	uint8_t compatible_id[8];
+	uint8_t uuid_format;
+	uint8_t uuid_length;
+} __packed ivrs_ivhd_f0_entry_t;
+
 #endif /* __ACPI_ACPI_IVRS_H__ */