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authorNico Huber <nico.h@gmx.de>2019-08-11 13:56:30 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-01-26 13:28:41 +0000
commit0c314f9c7e1b3c39ad8b4c1f7cf0f72bdcaf8ff1 (patch)
treed56d5916781b64e7045cc350283973cff5c73136 /src/include/acpi
parentdf4fa45ce4fe59ddd339e7837fefa504fb34cc40 (diff)
nb/intel/gm45: Wedge DDR2 SPD support in
Add initial support for DDR2. This also changes GM45 raminit to internally work in units of 1/256 ns for both DDR2 and DDR3 instead of the 1/8 ns MTB assumed for DDR3, which simplifies the handling of time values. DDR3 time values are thus scaled by a factor of 32 accordingly. TODO: - DDR2 JEDEC init - Memory IO init - Register programming TEST: DDR2 systems boot (with the rest of the patch train) - Tested on a Dell Latitude E6400 - Tested on a Compal JHL90 TEST: Ensure DDR3 systems still boot - Tested on a Thinkpad X200 Change-Id: I265938d58c30264fd5d4f7b89da7b689058b8cf8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34826 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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