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authorShuo Liu <shuo.liu@intel.com>2024-04-20 06:22:30 +0800
committerFelix Held <felix-coreboot@felixheld.de>2024-05-06 10:48:06 +0000
commit71814b0e5bedd01e6258afb26da72e28a49e0aae (patch)
treecf2db2a566ff633e45c19d2fd6a5f69762ee442c /src/include/acpi/acpigen_pci.h
parent63f975b68fc2b3a3e8c0717c7b292104e15f595c (diff)
acpi: Remove acpigen_write_OSC_pci_domain
For PCI domains, static _OSC will be used for better readability and maintenance. This reverts commit f4a12e1d39a097e17007ef11ccf784c2a42f1924. TEST=Build and boot on intel/archercity CRB Change-Id: I2e2b2f0533a3940caf2806ec1ed048c30e4ba801 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82032 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/acpi/acpigen_pci.h')
-rw-r--r--src/include/acpi/acpigen_pci.h11
1 files changed, 0 insertions, 11 deletions
diff --git a/src/include/acpi/acpigen_pci.h b/src/include/acpi/acpigen_pci.h
index 7a07423b7b..69216ec4fa 100644
--- a/src/include/acpi/acpigen_pci.h
+++ b/src/include/acpi/acpigen_pci.h
@@ -7,13 +7,6 @@
#include <device/pci_def.h>
#include <device/pci_type.h>
-#define PCIE_NATIVE_HOTPLUG_CONTROL 0x01
-#define SHPC_NATIVE_HOTPLUG_CONTROL 0x02
-#define PCIE_PME_CONTROL 0x04
-#define PCIE_AER_CONTROL 0x08
-#define PCIE_CAP_STRUCTURE_CONTROL 0x10
-#define PCIE_LTR_CONTROL 0x20
-
void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn);
void acpigen_write_ADR_pci_device(const struct device *dev);
@@ -23,8 +16,4 @@ void acpigen_write_PRT_source_entry(unsigned int pci_dev, unsigned int acpi_pin,
void pci_domain_fill_ssdt(const struct device *domain);
-void acpigen_write_OSC_pci_domain(const struct device *domain, const bool is_cxl_domain);
-uint32_t soc_get_granted_pci_features(const struct device *domain);
-uint32_t soc_get_granted_cxl_features(const struct device *domain);
-
#endif /* ACPIGEN_PCI_H */