diff options
| author | John Zhao <john.zhao@intel.com> | 2021-04-27 11:19:41 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-05-18 22:00:22 +0000 |
| commit | 8bb83a3456e05fb55c983484b3ace5d46f8bcfd7 (patch) | |
| tree | ee02ab2b7ef48dbeb9340dab836d4ec6fc946f9c /src/ec | |
| parent | 7e982b1dd9de4c8a4a534588f18d5e429389e52e (diff) | |
ec/google/chromeec: Provide EC access for Retimer firmware upgrade
coreboot needs to access EC RFWU entry in order to suspend and resume PD
and modes setting. This change adds ec_retimer_fw_update implementation
for retimer firmware upgrade.
BUG=b:186521258
TEST=Build image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ib937d8bd72fc39487854773573b435bf2add672a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52713
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/ec')
| -rw-r--r-- | src/ec/google/chromeec/ec_acpi.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 8cfc7b1953..4b3f78188b 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -241,3 +241,16 @@ const char *ec_retimer_fw_update_path(void) { return "\\_SB_.PCI0.LPCB.EC0_.RFWU"; } + +void ec_retimer_fw_update(uint8_t data) +{ + const char *RFWU = ec_retimer_fw_update_path(); + + /* + * Write the EC RAM for Retimer Upgrade + * RFWU = data + */ + acpigen_write_store(); + acpigen_write_byte(data); + acpigen_emit_namestring(RFWU); +} |