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authorWonkyu Kim <wonkyu.kim@intel.com>2020-01-09 23:34:03 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-01-18 11:18:38 +0000
commit69855f2e609483b2cbe4aebf7fa6ca1dde0bfc30 (patch)
tree4dc16b33d6c740564f0a84716d4ab260c49a493a /src/ec
parent97fa809f7cf0b1ba1832f3783b4ddffb823b75f4 (diff)
soc/intel/tigerlake: Update pci dev definition
This change updates pci dev definition according to TGL EDS. Add GSPI3 case in chip.c according to updated pci dev definitions. Reference TGL Process EDS#575681 rev1.0 TGL PCH EDS#576591 rev1.2 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38341 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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