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authorShaunak Saha <shaunak.saha@intel.com>2016-09-09 14:50:34 -0700
committerMartin Roth <martinroth@google.com>2016-09-15 01:19:50 +0200
commit563de15b8a4aafad162352754975158222f8de6c (patch)
treee5af5a14a12cdd1f3153a259bc49bbd948274ce9 /src/ec/smsc
parent16e9d459a09ae5833776e29926207d43d2fc9a02 (diff)
intel/amenia: Remove setting of GPIO_TIER1_SCI enable bit
This patch removes setting of gpio_tier1_sci_en from mainboard smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl now. BUG=chrome-os-partner:56483 TEST=System resumes from S3 on lidopen, powerbutton and USB wake. Also from S0iX system is resuming for WIFI wake. Change-Id: I066f0907a1c597e6fee09821910c59a8a90cccaa Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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